70#include "llvm/IR/IntrinsicsPowerPC.h"
105#define DEBUG_TYPE "ppc-lowering"
127 cl::desc(
"disable vector permute decomposition"),
131 "disable-auto-paired-vec-st",
132 cl::desc(
"disable automatically generated 32byte paired vector stores"),
138 "Number of shuffles lowered to a VPERM or XXPERM");
156 initializeAddrModeMap();
159 bool isPPC64 = Subtarget.
isPPC64();
168 if (!Subtarget.hasEFPU2())
193 if (Subtarget.isISA3_0()) {
223 if (!Subtarget.hasSPE()) {
239 if (Subtarget.useCRBits()) {
242 if (isPPC64 || Subtarget.hasFPCVT()) {
245 isPPC64 ? MVT::i64 : MVT::i32);
248 isPPC64 ? MVT::i64 : MVT::i32);
252 isPPC64 ? MVT::i64 : MVT::i32);
255 isPPC64 ? MVT::i64 : MVT::i32);
259 isPPC64 ? MVT::i64 : MVT::i32);
262 isPPC64 ? MVT::i64 : MVT::i32);
266 isPPC64 ? MVT::i64 : MVT::i32);
269 isPPC64 ? MVT::i64 : MVT::i32);
316 if (Subtarget.isISA3_0()) {
351 if (!Subtarget.hasSPE()) {
356 if (Subtarget.hasVSX()) {
361 if (Subtarget.hasFSQRT()) {
366 if (Subtarget.hasFPRND()) {
407 if (Subtarget.hasSPE()) {
415 if (Subtarget.hasSPE())
421 if (!Subtarget.hasFSQRT() &&
422 !(
TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
426 if (!Subtarget.hasFSQRT() &&
427 !(
TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
428 Subtarget.hasFRES()))
431 if (Subtarget.hasFCPSGN()) {
439 if (Subtarget.hasFPRND()) {
453 if (Subtarget.isISA3_1()) {
464 if (Subtarget.isISA3_0()) {
484 if (!Subtarget.useCRBits()) {
497 if (!Subtarget.useCRBits())
500 if (Subtarget.hasFPU()) {
511 if (!Subtarget.useCRBits())
516 if (Subtarget.hasSPE()) {
540 if (Subtarget.hasDirectMove() && isPPC64) {
545 if (
TM.Options.UnsafeFPMath) {
648 if (Subtarget.hasSPE()) {
670 if (Subtarget.has64BitSupport()) {
685 if (Subtarget.hasLFIWAX() || Subtarget.
isPPC64()) {
691 if (Subtarget.hasSPE()) {
701 if (Subtarget.hasFPCVT()) {
702 if (Subtarget.has64BitSupport()) {
723 if (Subtarget.use64BitRegs()) {
741 if (Subtarget.has64BitSupport()) {
748 if (Subtarget.hasVSX()) {
755 if (Subtarget.hasAltivec()) {
756 for (
MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
771 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
784 if (Subtarget.hasVSX()) {
790 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
800 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
874 if (!Subtarget.hasP8Vector()) {
916 if (Subtarget.hasAltivec())
917 for (
auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
920 if (Subtarget.hasP8Altivec())
931 if (Subtarget.hasVSX()) {
937 if (Subtarget.hasP8Altivec())
942 if (Subtarget.isISA3_1()) {
980 if (Subtarget.hasVSX()) {
983 if (Subtarget.hasP8Vector()) {
987 if (Subtarget.hasDirectMove() && isPPC64) {
1001 if (
TM.Options.UnsafeFPMath) {
1038 if (Subtarget.hasP8Vector())
1047 if (Subtarget.hasP8Altivec()) {
1074 if (Subtarget.isISA3_1())
1176 if (Subtarget.hasP8Altivec()) {
1181 if (Subtarget.hasP9Vector()) {
1186 if (Subtarget.useCRBits()) {
1245 }
else if (Subtarget.hasVSX()) {
1270 for (
MVT VT : {MVT::f32, MVT::f64}) {
1289 if (Subtarget.hasP9Altivec()) {
1290 if (Subtarget.isISA3_1()) {
1313 if (Subtarget.hasP10Vector()) {
1318 if (Subtarget.pairedVectorMemops()) {
1323 if (Subtarget.hasMMA()) {
1324 if (Subtarget.isISAFuture())
1333 if (Subtarget.has64BitSupport())
1336 if (Subtarget.isISA3_1())
1354 if (Subtarget.hasAltivec()) {
1381 if (Subtarget.hasFPCVT())
1384 if (Subtarget.useCRBits())
1393 if (Subtarget.useCRBits()) {
1422 setLibcallName(RTLIB::MEMCPY, isPPC64 ?
"___memmove64" :
"___memmove");
1423 setLibcallName(RTLIB::MEMMOVE, isPPC64 ?
"___memmove64" :
"___memmove");
1424 setLibcallName(RTLIB::MEMSET, isPPC64 ?
"___memset64" :
"___memset");
1425 setLibcallName(RTLIB::BZERO, isPPC64 ?
"___bzero64" :
"___bzero");
1430 if (Subtarget.useCRBits()) {
1527void PPCTargetLowering::initializeAddrModeMap() {
1582 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1584 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1593 for (
auto *EltTy : STy->elements()) {
1611 if (Subtarget.hasAltivec())
1613 return Alignment.
value();
1621 return Subtarget.hasSPE();
1645 return "PPCISD::FTSQRT";
1647 return "PPCISD::FSQRT";
1652 return "PPCISD::XXSPLTI_SP_TO_DP";
1654 return "PPCISD::XXSPLTI32DX";
1658 return "PPCISD::XXPERM";
1678 return "PPCISD::CALL_RM";
1680 return "PPCISD::CALL_NOP_RM";
1682 return "PPCISD::CALL_NOTOC_RM";
1687 return "PPCISD::BCTRL_RM";
1689 return "PPCISD::BCTRL_LOAD_TOC_RM";
1701 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1703 return "PPCISD::ANDI_rec_1_EQ_BIT";
1705 return "PPCISD::ANDI_rec_1_GT_BIT";
1720 return "PPCISD::ST_VSR_SCAL_INT";
1747 return "PPCISD::PADDI_DTPREL";
1763 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1765 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1775 return "PPCISD::STRICT_FADDRTZ";
1777 return "PPCISD::STRICT_FCTIDZ";
1779 return "PPCISD::STRICT_FCTIWZ";
1781 return "PPCISD::STRICT_FCTIDUZ";
1783 return "PPCISD::STRICT_FCTIWUZ";
1785 return "PPCISD::STRICT_FCFID";
1787 return "PPCISD::STRICT_FCFIDU";
1789 return "PPCISD::STRICT_FCFIDS";
1791 return "PPCISD::STRICT_FCFIDUS";
1794 return "PPCISD::STORE_COND";
1802 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1819 return CFP->getValueAPF().isZero();
1824 return CFP->getValueAPF().isZero();
1832 return Op < 0 ||
Op == Val;
1844 if (ShuffleKind == 0) {
1847 for (
unsigned i = 0; i != 16; ++i)
1850 }
else if (ShuffleKind == 2) {
1853 for (
unsigned i = 0; i != 16; ++i)
1856 }
else if (ShuffleKind == 1) {
1857 unsigned j =
IsLE ? 0 : 1;
1858 for (
unsigned i = 0; i != 8; ++i)
1875 if (ShuffleKind == 0) {
1878 for (
unsigned i = 0; i != 16; i += 2)
1882 }
else if (ShuffleKind == 2) {
1885 for (
unsigned i = 0; i != 16; i += 2)
1889 }
else if (ShuffleKind == 1) {
1890 unsigned j =
IsLE ? 0 : 2;
1891 for (
unsigned i = 0; i != 8; i += 2)
1912 if (!Subtarget.hasP8Vector())
1916 if (ShuffleKind == 0) {
1919 for (
unsigned i = 0; i != 16; i += 4)
1925 }
else if (ShuffleKind == 2) {
1928 for (
unsigned i = 0; i != 16; i += 4)
1934 }
else if (ShuffleKind == 1) {
1935 unsigned j =
IsLE ? 0 : 4;
1936 for (
unsigned i = 0; i != 8; i += 4)
1954 if (
N->getValueType(0) != MVT::v16i8)
1956 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1957 "Unsupported merge size!");
1959 for (
unsigned i = 0; i != 8/UnitSize; ++i)
1960 for (
unsigned j = 0; j != UnitSize; ++j) {
1979 if (ShuffleKind == 1)
1981 else if (ShuffleKind == 2)
1986 if (ShuffleKind == 1)
1988 else if (ShuffleKind == 0)
2004 if (ShuffleKind == 1)
2006 else if (ShuffleKind == 2)
2011 if (ShuffleKind == 1)
2013 else if (ShuffleKind == 0)
2064 if (
N->getValueType(0) != MVT::v16i8)
2067 for (
unsigned i = 0; i < 2; ++i)
2068 for (
unsigned j = 0; j < 4; ++j)
2095 if (ShuffleKind == 1)
2097 else if (ShuffleKind == 2)
2104 if (ShuffleKind == 1)
2106 else if (ShuffleKind == 0)
2122 if (
N->getValueType(0) != MVT::v16i8)
2129 for (i = 0; i != 16 &&
SVOp->getMaskElt(i) < 0; ++i)
2132 if (i == 16)
return -1;
2136 unsigned ShiftAmt =
SVOp->getMaskElt(i);
2137 if (ShiftAmt < i)
return -1;
2142 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2144 for (++i; i != 16; ++i)
2147 }
else if (ShuffleKind == 1) {
2149 for (++i; i != 16; ++i)
2156 ShiftAmt = 16 - ShiftAmt;
2165 EVT VT =
N->getValueType(0);
2166 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2167 return EltSize == 8 &&
N->getMaskElt(0) ==
N->getMaskElt(1);
2170 EltSize <= 8 &&
"Can only handle 1,2,4,8 byte element sizes");
2174 if (
N->getMaskElt(0) % EltSize != 0)
2187 for (
unsigned i = 1; i != EltSize; ++i)
2188 if (
N->getMaskElt(i) < 0 ||
N->getMaskElt(i) != (
int)(i+
ElementBase))
2191 for (
unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2192 if (
N->getMaskElt(i) < 0)
continue;
2193 for (
unsigned j = 0; j != EltSize; ++j)
2194 if (
N->getMaskElt(i+j) !=
N->getMaskElt(j))
2211 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2212 "Unexpected element width.");
2217 for (
unsigned i = 0; i <
NumOfElem; ++i) {
2218 MaskVal[0] =
N->getMaskElt(i * Width);
2225 for (
unsigned int j = 1; j < Width; ++j) {
2226 MaskVal[j] =
N->getMaskElt(i * Width + j);
2242 unsigned M0 =
N->getMaskElt(0) / 4;
2243 unsigned M1 =
N->getMaskElt(4) / 4;
2244 unsigned M2 =
N->getMaskElt(8) / 4;
2245 unsigned M3 =
N->getMaskElt(12) / 4;
2252 if ((
M0 > 3 &&
M1 == 1 &&
M2 == 2 &&
M3 == 3) ||
2253 (
M0 < 4 &&
M1 == 5 &&
M2 == 6 &&
M3 == 7)) {
2260 if ((
M1 > 3 &&
M0 == 0 &&
M2 == 2 &&
M3 == 3) ||
2261 (
M1 < 4 &&
M0 == 4 &&
M2 == 6 &&
M3 == 7)) {
2268 if ((
M2 > 3 &&
M0 == 0 &&
M1 == 1 &&
M3 == 3) ||
2269 (
M2 < 4 &&
M0 == 4 &&
M1 == 5 &&
M3 == 7)) {
2276 if ((
M3 > 3 &&
M0 == 0 &&
M1 == 1 &&
M2 == 2) ||
2277 (
M3 < 4 &&
M0 == 4 &&
M1 == 5 &&
M2 == 6)) {
2286 if (
N->getOperand(1).isUndef()) {
2312 bool &Swap,
bool IsLE) {
2313 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2319 unsigned M0 =
N->getMaskElt(0) / 4;
2320 unsigned M1 =
N->getMaskElt(4) / 4;
2321 unsigned M2 =
N->getMaskElt(8) / 4;
2322 unsigned M3 =
N->getMaskElt(12) / 4;
2326 if (
N->getOperand(1).isUndef()) {
2327 assert(
M0 < 4 &&
"Indexing into an undef vector?");
2328 if (
M1 != (
M0 + 1) % 4 ||
M2 != (
M1 + 1) % 4 ||
M3 != (
M2 + 1) % 4)
2337 if (
M1 != (
M0 + 1) % 8 ||
M2 != (
M1 + 1) % 8 ||
M3 != (
M2 + 1) % 8)
2341 if (
M0 == 0 ||
M0 == 7 ||
M0 == 6 ||
M0 == 5) {
2347 }
else if (
M0 == 4 ||
M0 == 3 ||
M0 == 2 ||
M0 == 1) {
2357 if (
M0 == 0 ||
M0 == 1 ||
M0 == 2 ||
M0 == 3) {
2362 }
else if (
M0 == 4 ||
M0 == 5 ||
M0 == 6 ||
M0 == 7) {
2374 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2379 for (
int i = 0; i < 16; i += Width)
2380 if (
N->getMaskElt(i) != i + Width - 1)
2411 bool &Swap,
bool IsLE) {
2412 assert(
N->getValueType(0) == MVT::v16i8 &&
"Shuffle vector expects v16i8");
2418 unsigned M0 =
N->getMaskElt(0) / 8;
2419 unsigned M1 =
N->getMaskElt(8) / 8;
2420 assert(((
M0 |
M1) < 4) &&
"A mask element out of bounds?");
2424 if (
N->getOperand(1).isUndef()) {
2425 if ((
M0 |
M1) < 2) {
2426 DM =
IsLE ? (((~M1) & 1) << 1) + ((~
M0) & 1) : (
M0 << 1) + (
M1 & 1);
2434 if (
M0 > 1 &&
M1 < 2) {
2444 DM = (((~M1) & 1) << 1) + ((~
M0) & 1);
2449 }
else if (
M0 > 1 &&
M1 < 2) {
2457 DM = (
M0 << 1) + (
M1 & 1);
2470 EVT VT =
SVOp->getValueType(0);
2472 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2474 :
SVOp->getMaskElt(0);
2477 return (16 / EltSize) - 1 - (
SVOp->getMaskElt(0) / EltSize);
2479 return SVOp->getMaskElt(0) / EltSize;
2493 unsigned EltSize = 16/
N->getNumOperands();
2494 if (EltSize < ByteSize) {
2495 unsigned Multiple = ByteSize/EltSize;
2500 for (
unsigned i = 0, e =
N->getNumOperands(); i != e; ++i) {
2501 if (
N->getOperand(i).isUndef())
continue;
2519 for (
unsigned i = 0; i !=
Multiple-1; ++i) {
2545 for (
unsigned i = 0, e =
N->getNumOperands(); i != e; ++i) {
2546 if (
N->getOperand(i).isUndef())
continue;
2547 if (!
OpVal.getNode())
2548 OpVal =
N->getOperand(i);
2549 else if (
OpVal !=
N->getOperand(i))
2560 assert(
CN->getValueType(0) == MVT::f32 &&
"Only one legal FP vector type!");
2599 if (
N->getValueType(0) == MVT::i32)
2630 if (
Memop->getMemoryVT() == MVT::f64) {
2631 Base =
N.getOperand(0);
2680 Base =
N.getOperand(0);
2683 }
else if (
N.getOpcode() ==
ISD::OR) {
2693 if (
LHSKnown.Zero.getBoolValue()) {
2698 Base =
N.getOperand(0);
2775 Base =
N.getOperand(0);
2778 }
else if (
N.getOperand(1).getOpcode() ==
PPCISD::Lo) {
2781 &&
"Cannot handle constant offsets yet!");
2787 Base =
N.getOperand(0);
2790 }
else if (
N.getOpcode() ==
ISD::OR) {
2807 Base =
N.getOperand(0);
2823 CN->getValueType(0));
2828 if ((
CN->getValueType(0) == MVT::i32 ||
2829 (int64_t)
CN->getZExtValue() == (
int)
CN->getZExtValue()) &&
2832 int Addr = (int)
CN->getZExtValue();
2839 unsigned Opc =
CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2860 if (
N.getValueType() != MVT::i64)
2922 !
N.getOperand(1).hasOneUse() || !
N.getOperand(0).hasOneUse())) {
2923 Base =
N.getOperand(0);
2968 if (!
MemVT.isSimple())
2970 switch(
MemVT.getSimpleVT().SimpleTy) {
2974 if (!ST.hasP8Vector())
2979 if (!ST.hasP9Vector())
2992 if (UI.getUse().get().getResNo() == 0 &&
3014 Ptr = LD->getBasePtr();
3015 VT = LD->getMemoryVT();
3016 Alignment = LD->getAlign();
3018 Ptr = ST->getBasePtr();
3019 VT = ST->getMemoryVT();
3020 Alignment = ST->getAlign();
3059 if (VT != MVT::i64) {
3064 if (Alignment <
Align(4))
3074 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3133 const bool Is64Bit = Subtarget.
isPPC64();
3134 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3164 return getTOCEntry(DAG,
SDLoc(CP),
GA);
3174 return getTOCEntry(DAG,
SDLoc(CP),
GA);
3252 return getTOCEntry(DAG,
SDLoc(JT),
GA);
3311 return LowerGlobalTLSAddressAIX(
Op, DAG);
3313 return LowerGlobalTLSAddressLinux(
Op, DAG);
3326 bool Is64Bit = Subtarget.
isPPC64();
3384 bool is64bit = Subtarget.
isPPC64();
3432 if (!
TM.isPositionIndependent())
3528 return getTOCEntry(DAG,
DL,
GA);
3539 return getTOCEntry(DAG,
DL,
GA);
3561 if (
LHSVT == MVT::f128) {
3562 assert(!Subtarget.hasP9Vector() &&
3563 "SETCC for f128 is already legal under Power9!");
3576 if (
Op.getValueType() == MVT::v2i64) {
3579 if (LHS.getValueType() == MVT::v2i64) {
3587 int ShuffV[] = {1, 0, 3, 2};
3609 if (
C->isAllOnes() ||
C->isZero())
3619 EVT VT =
Op.getValueType();
3628 EVT VT =
Node->getValueType(0);
3642 if (VT == MVT::i64) {
3686 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3701 DAG.getConstant(VT ==
MVT::
i64 ? 2 : 1, dl,
3726 assert(!Subtarget.
isPPC64() &&
"LowerVACOPY is PPC32 only");
3741 return Op.getOperand(0);
3750 "Expecting Inline ASM node.");
3760 if (
Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
3782 if (Reg != PPC::LR && Reg != PPC::LR8)
3807 bool isPPC64 = (
PtrVT == MVT::i64);
3813 Entry.
Ty = IntPtrTy;
3814 Entry.Node =
Trmp;
Args.push_back(Entry);
3817 Entry.Node = DAG.
getConstant(isPPC64 ? 48 : 40, dl,
3819 Args.push_back(Entry);
3821 Entry.Node =
FPtr;
Args.push_back(Entry);
3822 Entry.Node =
Nest;
Args.push_back(Entry);
3826 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3920static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3921 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3922 PPC::F11, PPC::F12, PPC::F13};
3929 if (Flags.isByVal())
3930 ArgSize = Flags.getByValSize();
3934 if (!Flags.isInConsecutiveRegs())
3948 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3949 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3950 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3951 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3952 Alignment =
Align(16);
3955 if (Flags.isByVal()) {
3956 auto BVAlign = Flags.getNonZeroByValAlign();
3960 "ByVal alignment is not a multiple of the pointer size");
3967 if (Flags.isInConsecutiveRegs()) {
3971 if (Flags.isSplit() &&
OrigVT != MVT::ppcf128)
4002 if (Flags.isInConsecutiveRegsLast())
4011 if (!Flags.isByVal()) {
4012 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
4017 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4018 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4019 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
4020 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
4033 unsigned NumBytes) {
4037SDValue PPCTargetLowering::LowerFormalArguments(
4042 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
4045 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
4048 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
4052SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
4103 CCInfo.AllocateStack(LinkageSize,
PtrAlign);
4105 CCInfo.PreAnalyzeFormalArguments(Ins);
4108 CCInfo.clearWasPPCF128();
4110 for (
unsigned i = 0, e =
ArgLocs.size(); i !=
e; ++i) {
4114 if (
VA.isRegLoc()) {
4116 EVT ValVT =
VA.getValVT();
4123 RC = &PPC::GPRCRegClass;
4126 if (Subtarget.hasP8Vector())
4127 RC = &PPC::VSSRCRegClass;
4128 else if (Subtarget.hasSPE())
4129 RC = &PPC::GPRCRegClass;
4131 RC = &PPC::F4RCRegClass;
4134 if (Subtarget.hasVSX())
4135 RC = &PPC::VSFRCRegClass;
4136 else if (Subtarget.hasSPE())
4138 RC = &PPC::GPRCRegClass;
4140 RC = &PPC::F8RCRegClass;
4145 RC = &PPC::VRRCRegClass;
4148 RC = &PPC::VRRCRegClass;
4152 RC = &PPC::VRRCRegClass;
4159 if (
VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
4160 assert(i + 1 < e &&
"No second half of double precision argument");
4172 ValVT == MVT::i1 ? MVT::i32 : ValVT);
4173 if (ValVT == MVT::i1)
4177 InVals.push_back(ArgValue);
4183 unsigned ArgSize =
VA.getLocVT().getStoreSize();
4185 unsigned ObjSize =
VA.getValVT().getStoreSize();
4211 unsigned MinReservedArea =
CCByValInfo.getStackSize();
4212 MinReservedArea = std::max(MinReservedArea, LinkageSize);
4228 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4229 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4234 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
4250 PtrVT.getSizeInBits() / 8, CCInfo.getStackSize(),
true));
4306 const SDLoc &dl)
const {
4310 else if (Flags.isZExt())
4317SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4330 "fastcc not supported on varargs functions");
4340 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4341 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4344 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4345 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4360 unsigned NumBytes = LinkageSize;
4363 for (
unsigned i = 0, e =
Ins.size(); i !=
e; ++i) {
4364 if (Ins[i].Flags.isNest())
4382 for (
unsigned ArgNo = 0, e =
Ins.size(); ArgNo !=
e; ++ArgNo) {
4390 if (Ins[ArgNo].isOrigArg()) {
4417 if (Flags.isByVal()) {
4418 assert(Ins[ArgNo].isOrigArg() &&
"Byval arguments cannot be implicit");
4424 ObjSize = Flags.getByValSize();
4436 InVals.push_back(
FIN);
4459 if (!isLittleEndian) {
4463 InVals.push_back(
Arg);
4483 InVals.push_back(
FIN);
4510 switch (
ObjectVT.getSimpleVT().SimpleTy) {
4515 if (Flags.isNest()) {
4559 Subtarget.hasP8Vector()
4560 ? &PPC::VSSRCRegClass
4564 ? &PPC::VSFRCRegClass
4583 DAG.getConstant(32, dl,
MVT::
i32));
4601 if (Flags.isInConsecutiveRegsLast())
4640 InVals.push_back(
ArgVal);
4644 unsigned MinReservedArea;
4648 MinReservedArea = LinkageSize;
4696 unsigned ParamSize) {
4698 if (!isTailCall)
return 0;
4720 "PC Relative callers do not have a TOC and cannot share a TOC Base");
4733 if (!
TM.shouldAssumeDSOLocal(*Caller->getParent(),
CalleeGV))
4758 if (
STICallee->isUsingPCRelativeCalls())
4765 if (!
CalleeGV->isStrongDefinitionForLinker())
4778 if (
TM.getFunctionSections() ||
CalleeGV->hasComdat() ||
4779 Caller->hasComdat() ||
CalleeGV->getSection() != Caller->getSection())
4782 if (
F->getSectionPrefix() != Caller->getSectionPrefix())
4798 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4799 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4802 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4803 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4806 const unsigned NumGPRs = std::size(GPR);
4808 const unsigned NumVRs = std::size(VR);
4811 unsigned NumBytes = LinkageSize;
4816 if (Param.Flags.isNest())
continue;
4873bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4884 if (isVarArg)
return false;
4960bool PPCTargetLowering::IsEligibleForTailCallOptimization(
4983 return CalleeGV->hasHiddenVisibility() ||
4984 CalleeGV->hasProtectedVisibility();
4994 if (!
C)
return nullptr;
4996 int Addr =
C->getZExtValue();
4997 if ((
Addr & 3) != 0 ||
5003 (
int)
C->getZExtValue() >> 2,
SDLoc(
Op),
5010struct TailCallArgumentInfo {
5015 TailCallArgumentInfo() =
default;
5025 for (
unsigned i = 0, e =
TailCallArgs.size(); i != e; ++i) {
5046 bool isPPC64 = Subtarget.
isPPC64();
5047 int SlotSize = isPPC64 ? 8 : 4;
5051 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5068 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5070 TailCallArgumentInfo
Info;
5072 Info.FrameIdxOp =
FIN;
5080SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5085 EVT VT = Subtarget.
isPPC64() ? MVT::i64 : MVT::i32;
5086 LROpOut = getReturnAddrFrameIndex(DAG);
5104 Flags.getNonZeroByValAlign(),
false,
false,
false,
5169SDValue PPCTargetLowering::LowerCallResult(
5183 for (
unsigned i = 0, e =
RVLocs.size(); i !=
e; ++i) {
5185 assert(
VA.isRegLoc() &&
"Can only return in registers!");
5189 if (Subtarget.hasSPE() &&
VA.getLocVT() == MVT::f64) {
5209 switch (
VA.getLocInfo()) {
5227 InVals.push_back(Val);
5374 const char *SymName = S->getSymbol();
5408 "Expected a CALLSEQ_STARTSDNode.");
5414 if (
LastValue.getValueType() != MVT::Glue)
5426 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5467 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5482 const MVT RegVT = Subtarget.
isPPC64() ? MVT::i64 : MVT::i32;
5487 Alignment, MMOFlags);
5507 Chain =
TOCVal.getValue(0);
5513 "Nest parameter is not supported on AIX.");
5516 Chain =
EnvVal.getValue(0);
5532 const bool IsPPC64 = Subtarget.
isPPC64();
5534 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5537 Ops.push_back(Chain);
5543 assert(!
CFlags.IsPatchPoint &&
"Patch point calls are not indirect.");
5572 Ops.push_back(DAG.
getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5581 for (
unsigned i = 0, e =
RegsToPass.size(); i != e; ++i)
5594 Ops.push_back(DAG.
getRegister(PPC::CR1EQ, MVT::i32));
5600 assert(Mask &&
"Missing call preserved mask for calling convention");
5605 Ops.push_back(
Glue);
5608SDValue PPCTargetLowering::FinishCall(
5627 dl,
CFlags.HasNest, Subtarget);
5646 "Expecting a global address, external symbol, absolute value, "
5647 "register or an indirect tail call when PC Relative calls are "
5651 "Unexpected call opcode for a tail call.");
5658 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5674 return LowerCallResult(Chain,
Glue,
CFlags.CallConv,
CFlags.IsVarArg, Ins, dl,
5699bool PPCTargetLowering::isEligibleForTCO(
5709 return IsEligibleForTailCallOptimization_64SVR4(
5741 isEligibleForTCO(GV, CallConv,
CallerCC, CB, isVarArg, Outs, Ins,
5756 "Callee should be an llvm::Function object.");
5759 <<
"\nTCO callee: ");
5766 "site marked musttail");
5784 return LowerCall_AIX(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5789 return LowerCall_64SVR4(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5791 return LowerCall_32SVR4(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5795SDValue PPCTargetLowering::LowerCall_32SVR4(
5806 const bool IsVarArg =
CFlags.IsVarArg;
5807 const bool IsTailCall =
CFlags.IsTailCall;
5838 CCInfo.PreAnalyzeCallOperands(Outs);
5844 unsigned NumArgs = Outs.size();
5846 for (
unsigned i = 0; i != NumArgs; ++i) {
5847 MVT ArgVT = Outs[i].VT;
5851 if (Outs[i].IsFixed) {
5861 errs() <<
"Call operand #" << i <<
" has unhandled type "
5871 CCInfo.clearWasPPCF128();
5899 Chain = EmitTailCallLoadFPAndRetAddr(DAG,
SPDiff, Chain,
LROp,
FPOp, dl);
5922 if (Flags.isByVal()) {
5962 if (
Arg.getValueType() == MVT::i1)
5966 if (
VA.isRegLoc()) {
5969 if (Subtarget.hasSPE() &&
Arg.getValueType() == MVT::f64) {
6006 for (
unsigned i = 0, e =
RegsToPass.size(); i !=
e; ++i) {
6034SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
6041 int64_t FrameSize =
CallSeqStart.getConstantOperandVal(1);
6049SDValue PPCTargetLowering::LowerCall_64SVR4(
6058 unsigned NumOps = Outs.size();
6079 "fastcc not supported on varargs functions");
6086 unsigned NumBytes = LinkageSize;
6090 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6091 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
6094 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
6095 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
6098 const unsigned NumGPRs = std::size(GPR);
6100 const unsigned NumVRs = std::size(VR);
6112 for (
unsigned i = 0; i != NumOps; ++i) {
6113 if (Outs[i].Flags.isNest())
continue;
6131 for (
unsigned i = 0; i != NumOps; ++i) {
6133 EVT ArgVT = Outs[i].VT;
6140 if (Flags.isByVal()) {
6183 if (Flags.isInConsecutiveRegsLast())
6198 NumBytes = std::max(NumBytes, LinkageSize + 8 *
PtrByteSize);
6200 NumBytes = LinkageSize;
6227 Chain = EmitTailCallLoadFPAndRetAddr(DAG,
SPDiff, Chain,
LROp,
FPOp, dl);
6244 for (
unsigned i = 0; i != NumOps; ++i) {
6247 EVT ArgVT = Outs[i].VT;
6277 if (
Arg.getValueType() == MVT::i32 ||
Arg.getValueType() == MVT::i1) {
6286 if (Flags.isByVal()) {
6292 unsigned Size = Flags.getByValSize();
6318 if (!isLittleEndian) {
6351 if (!isLittleEndian) {
6392 switch (
Arg.getSimpleValueType().SimpleTy) {
6397 if (Flags.isNest()) {
6413 "Parameter area must exist to pass an argument in memory.");
6454 if (
Arg.getValueType() != MVT::f32) {
6458 }
else if (!Flags.isInConsecutiveRegs()) {
6468 if (!isLittleEndian)
6473 }
else if (Flags.isInConsecutiveRegsLast()) {
6476 if (!isLittleEndian)
6493 if (
Arg.getValueType() == MVT::f32 &&
6494 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
6500 "Parameter area must exist to pass an argument in memory.");
6512 Flags.isInConsecutiveRegs()) ? 4 : 8;
6513 if (Flags.isInConsecutiveRegsLast())
6536 "Parameter area must exist if we have a varargs call.");
6570 "Parameter area must exist to pass an argument in memory.");
6585 "mismatch in size of parameter area");
6598 assert(!
CFlags.IsTailCall &&
"Indirect tails calls not supported");
6613 if (isELFv2ABI && !
CFlags.IsPatchPoint)
6620 for (
unsigned i = 0, e =
RegsToPass.size(); i !=
e; ++i) {
6638 "Required alignment greater than stack alignment.");
6672 State.getMachineFunction().getSubtarget());
6673 const bool IsPPC64 = Subtarget.
isPPC64();
6675 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
6677 if (ValVT == MVT::f128)
6684 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
6685 PPC::R7, PPC::R8, PPC::R9, PPC::R10};
6687 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6688 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
6691 PPC::V2, PPC::V3, PPC::V4, PPC::V5,
6692 PPC::V6, PPC::V7, PPC::V8, PPC::V9,
6693 PPC::V10, PPC::V11, PPC::V12, PPC::V13};
6698 "register width are not supported.");
6706 State.getStackSize(), RegVT, LocInfo));
6714 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32))
6732 assert(IsPPC64 &&
"PPC32 should have split i64 values.");
6741 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32))
6755 State.AllocateStack(IsPPC64 ? 8 : StoreSize,
Align(4));
6756 unsigned FReg = State.AllocateReg(
FPR);
6761 for (
unsigned I = 0;
I < StoreSize;
I +=
PtrAlign.value()) {
6762 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32)) {
6763 assert(FReg &&
"An FPR should be available when a GPR is reserved.");
6764 if (State.isVarArg()) {
6796 const unsigned VecSize = 16;
6797 const Align VecAlign(VecSize);
6799 if (!State.isVarArg()) {
6802 if (
unsigned VReg = State.AllocateReg(VR)) {
6809 const unsigned Offset = State.AllocateStack(VecSize, VecAlign);
6814 const unsigned PtrSize = IsPPC64 ? 8 : 4;
6823 unsigned Reg = State.AllocateReg(
GPRs);
6825 assert(Reg &&
"Allocating register unexpectedly failed.");
6834 if (State.isFixed(ValNo)) {
6835 if (
unsigned VReg = State.AllocateReg(VR)) {
6838 for (
unsigned I = 0;
I != VecSize;
I +=
PtrSize)
6839 State.AllocateReg(
GPRs);
6840 State.AllocateStack(VecSize, VecAlign);
6844 const unsigned Offset = State.AllocateStack(VecSize, VecAlign);
6851 const unsigned Offset = State.AllocateStack(VecSize, VecAlign);
6860 const unsigned Offset = State.AllocateStack(VecSize, VecAlign);
6864 const unsigned FirstReg = State.AllocateReg(PPC::R9);
6865 const unsigned SecondReg = State.AllocateReg(PPC::R10);
6867 "Allocating R9 or R10 unexpectedly failed.");
6878 const unsigned Offset = State.AllocateStack(VecSize, VecAlign);
6881 for (
unsigned I = 0;
I != VecSize;
I +=
PtrSize) {
6882 const unsigned Reg = State.AllocateReg(
GPRs);
6883 assert(Reg &&
"Failed to allocated register for vararg vector argument");
6899 "i64 should have been split for 32-bit codegen.");
6907 return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6909 return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass;
6911 return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass;
6919 return &PPC::VRRCRegClass;
6932 else if (Flags.isZExt())
6942 if (PPC::GPRCRegClass.
contains(Reg)) {
6943 assert(Reg >= PPC::R3 && Reg <= PPC::R10 &&
6944 "Reg must be a valid argument register!");
6945 return LASize + 4 * (Reg - PPC::R3);
6948 if (PPC::G8RCRegClass.
contains(Reg)) {
6949 assert(Reg >= PPC::X3 && Reg <= PPC::X10 &&
6950 "Reg must be a valid argument register!");
6951 return LASize + 8 * (Reg - PPC::X3);
6997SDValue PPCTargetLowering::LowerFormalArguments_AIX(
7004 "Unexpected calling convention!");
7014 const bool IsPPC64 = Subtarget.
isPPC64();
7028 CCInfo.AnalyzeFormalArguments(Ins,
CC_AIX);
7034 MVT LocVT =
VA.getLocVT();
7035 MVT ValVT =
VA.getValVT();
7050 "Object size is larger than size of MemLoc");
7056 const bool IsImmutable =
7063 InVals.push_back(ArgValue);
7069 if (
VA.isMemLoc() &&
VA.needsCustom()) {
7071 assert(isVarArg &&
"Only use custom memloc for vararg.");
7079 "Missing custom RegLoc.");
7082 "Unexpected Val type for custom RegLoc.");
7084 "ValNo mismatch between custom MemLoc and RegLoc.");
7088 Subtarget.hasVSX()));
7102 "Only 2 custom RegLocs expected for 64-bit codegen.");
7110 if (
VA.isRegLoc()) {
7111 if (
VA.getValVT().isScalarInteger())
7113 else if (
VA.getValVT().isFloatingPoint() && !
VA.getValVT().isVector()) {
7114 switch (
VA.getValVT().SimpleTy) {
7124 }
else if (
VA.getValVT().isVector()) {
7125 switch (
VA.getValVT().SimpleTy) {
7147 if (Flags.isByVal() &&
VA.isMemLoc()) {
7148 const unsigned Size =
7152 Size,
VA.getLocMemOffset(),
false,
7155 InVals.push_back(
FIN);
7160 if (Flags.isByVal()) {
7161 assert(
VA.isRegLoc() &&
"MemLocs should already be handled.");
7174 InVals.push_back(
FIN);
7178 IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7193 CopyFrom.
getValue(1), dl, CopyFrom,
7206 "RegLocs should be for ByVal argument.");
7213 if (
Offset != StackSize) {
7215 "Expected MemLoc for remaining bytes.");
7216 assert(
ArgLocs[
I].isMemLoc() &&
"Expected MemLoc for remaining bytes.");
7225 if (
VA.isRegLoc() && !
VA.needsCustom()) {
7230 Subtarget.hasVSX()));
7237 InVals.push_back(ArgValue);
7240 if (
VA.isMemLoc()) {
7265 static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,
7266 PPC::R7, PPC::R8, PPC::R9, PPC::R10};
7268 static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
7269 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
7276 (CCInfo.getStackSize() - LinkageSize) /
PtrByteSize;
7299SDValue PPCTargetLowering::LowerCall_AIX(
7312 "Unexpected calling convention!");
7329 const bool IsPPC64 = Subtarget.
isPPC64();
7333 CCInfo.AnalyzeCallOperands(Outs,
CC_AIX);
7342 const unsigned NumBytes = std::max<unsigned>(
7359 for (
unsigned I = 0,
E =
ArgLocs.size();
I !=
E;) {
7360 const unsigned ValNo =
ArgLocs[
I].getValNo();
7364 if (Flags.isByVal()) {
7365 const unsigned ByValSize = Flags.getByValSize();
7391 "Unexpected location for pass-by-value argument.");
7400 "Expected additional location for by-value argument.");
7412 DAG.getObjectPtrOffset(dl,
StackPtr,
7425 "Unexpected register residue for by-value argument.");
7440 assert(
PtrVT.getSimpleVT().getSizeInBits() > (Bytes * 8) &&
7441 "Unexpected load emitted during handling of pass-by-value "
7443 unsigned NumSHLBits =
PtrVT.getSimpleVT().getSizeInBits() - (Bytes * 8);
7460 const MVT LocVT =
VA.getLocVT();
7461 const MVT ValVT =
VA.getValVT();
7463 switch (
VA.getLocInfo()) {
7476 if (
VA.isRegLoc() && !
VA.needsCustom()) {
7483 if (
VA.isMemLoc() &&
VA.needsCustom() && ValVT.
isVector()) {
7484 assert(
CFlags.IsVarArg &&
"Custom MemLocs only used for Vector args.");
7496 assert(
I !=
E &&
"Unexpected end of CCvalAssigns.");
7498 "Expected custom RegLoc.");
7501 "Custom MemLoc ValNo and custom RegLoc ValNo must match.");
7519 "Only 2 custom RegLocs expected for 64-bit codegen.");
7527 if (
VA.isMemLoc()) {
7539 "Unexpected register handling for calling convention.");
7545 "Custom register handling only expected for VarArg.");
7554 else if (
Arg.getValueType().getFixedSizeInBits() <
7562 assert(
Arg.getValueType() == MVT::f64 &&
CFlags.IsVarArg && !IsPPC64 &&
7563 "Unexpected custom register for argument!");
7575 assert(
PeekArg.needsCustom() &&
"A second custom GPR is expected.");
7590 assert(!
CFlags.IsTailCall &&
"Indirect tail-calls not supported.");
7594 const unsigned TOCSaveOffset =
7627 return CCInfo.CheckReturn(
7642 CCInfo.AnalyzeReturn(Outs,
7653 assert(
VA.isRegLoc() &&
"Can only return in registers!");
7657 switch (
VA.getLocInfo()) {
7670 if (Subtarget.hasSPE() &&
VA.getLocVT() == MVT::f64) {
7699PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(
SDValue Op,
7724 bool isPPC64 = Subtarget.
isPPC64();
7725 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
7745 bool isPPC64 = Subtarget.
isPPC64();
7766PPCTargetLowering::getFramePointerFrameIndex(
SelectionDAG & DAG)
const {
7768 bool isPPC64 = Subtarget.
isPPC64();
7814 bool isPPC64 = Subtarget.
isPPC64();
7826 Op.getOperand(0),
Op.getOperand(1));
7833 Op.getOperand(0),
Op.getOperand(1));
7837 if (
Op.getValueType().isVector())
7838 return LowerVectorLoad(
Op, DAG);
7840 assert(
Op.getValueType() == MVT::i1 &&
7841 "Custom lowering only for i1 loads");
7854 BasePtr, MVT::i8, MMO);
7862 if (
Op.getOperand(1).getValueType().isVector())
7863 return LowerVectorStore(
Op, DAG);
7865 assert(
Op.getOperand(1).getValueType() == MVT::i1 &&
7866 "Custom lowering only for i1 stores");
7885 assert(
Op.getValueType() == MVT::i1 &&
7886 "Custom lowering only for i1 results");
7915 assert(
TrgVT.isVector() &&
"Vector type expected.");
7928 SrcVT.getVectorElementType().getSizeInBits()))
7930 if (
SrcSize == 256 &&
SrcVT.getVectorNumElements() < 2)
7941 N1.getValueType().getHalfNumVectorElementsVT(*DAG.
getContext());
7979 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
7986 if (!Subtarget.hasP9Vector() &&
CmpVT == MVT::f128) {
7995 if (!
CmpVT.isFloatingPoint() || !
TV.getValueType().isFloatingPoint() ||
8003 if (Subtarget.hasP9Vector() && LHS ==
TV && RHS ==
FV) {
8034 if (LHS.getValueType() == MVT::f32)
8037 if (
Sel1.getValueType() == MVT::f32)
8047 if (LHS.getValueType() == MVT::f32)
8056 if (LHS.getValueType() == MVT::f32)
8070 if (
Cmp.getValueType() == MVT::f32)
8073 if (
Sel1.getValueType() == MVT::f32)
8080 if (
Cmp.getValueType() == MVT::f32)
8086 if (
Cmp.getValueType() == MVT::f32)
8092 if (
Cmp.getValueType() == MVT::f32)
8098 if (
Cmp.getValueType() == MVT::f32)
8143 assert(Src.getValueType().isFloatingPoint() &&
8146 "Invalid FP_TO_INT types");
8147 if (Src.getValueType() == MVT::f32) {
8151 DAG.
getVTList(MVT::f64, MVT::Other), {Chain, Src}, Flags);
8152 Chain = Src.getValue(1);
8156 if ((
DestTy == MVT::i8 ||
DestTy == MVT::i16) && Subtarget.hasP9Vector())
8159 switch (
DestTy.SimpleTy) {
8166 assert((IsSigned || Subtarget.hasFPCVT()) &&
8167 "i64 FP_TO_UINT is supported only with FPCVT");
8170 EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64;
8182void PPCTargetLowering::LowerFP_TO_INTForReuse(
SDValue Op, ReuseLoadInfo &
RLI,
8184 const SDLoc &dl)
const {
8191 bool i32Stack =
Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
8192 (IsSigned || Subtarget.hasFPCVT());
8203 Alignment =
Align(4);
8208 DAG.
getVTList(MVT::Other), Ops, MVT::i32, MMO);
8210 Chain = DAG.
getStore(Chain, dl, Tmp,
FIPtr, MPI, Alignment);
8214 if (
Op.getValueType() == MVT::i32 && !
i32Stack) {
8223 RLI.Alignment = Alignment;
8231 const SDLoc &dl)
const {
8234 if (
Op->isStrictFPOpcode())
8241 const SDLoc &dl)
const {
8250 if (
SrcVT == MVT::f128)
8251 return Subtarget.hasP9Vector() ?
Op :
SDValue();
8255 if (
SrcVT == MVT::ppcf128) {
8256 if (
DstVT == MVT::i32) {
8272 {Op.getOperand(0), Lo, Hi}, Flags);
8275 {Res.getValue(1), Res}, Flags);
8297 Chain =
Sel.getValue(1);
8305 {Chain, Src, FltOfs}, Flags);
8309 {Chain, Val}, Flags);
8310 Chain =
SInt.getValue(1);
8330 if (Subtarget.hasDirectMove() && Subtarget.
isPPC64())
8331 return LowerFP_TO_INTDirectMove(
Op, DAG, dl);
8334 LowerFP_TO_INTForReuse(
Op,
RLI, DAG, dl);
8337 RLI.Alignment,
RLI.MMOFlags(),
RLI.AAInfo,
RLI.Ranges);
8353 if (
Op->isStrictFPOpcode())
8358 (Subtarget.hasFPCVT() ||
Op.getValueType() == MVT::i32);
8362 Op.getOperand(0).getValueType())) {
8364 LowerFP_TO_INTForReuse(
Op,
RLI, DAG, dl);
8369 if (!LD ||
LD->getExtensionType() !=
ET ||
LD->isVolatile() ||
8370 LD->isNonTemporal())
8372 if (
LD->getMemoryVT() !=
MemVT)
8382 RLI.Ptr =
LD->getBasePtr();
8383 if (
LD->isIndexed() && !
LD->getOffset().isUndef()) {
8385 "Non-pre-inc AM on PPC?");
8390 RLI.Chain =
LD->getChain();
8391 RLI.MPI =
LD->getPointerInfo();
8392 RLI.IsDereferenceable =
LD->isDereferenceable();
8393 RLI.IsInvariant =
LD->isInvariant();
8394 RLI.Alignment =
LD->getAlign();
8395 RLI.AAInfo =
LD->getAAInfo();
8396 RLI.Ranges =
LD->getRanges();
8406void PPCTargetLowering::spliceIntoChain(
SDValue ResChain,
8417 "A new TF really is required here");
8426bool PPCTargetLowering::directMoveIsProfitable(
const SDValue &
Op)
const {
8427 SDNode *Origin =
Op.getOperand(
Op->isStrictFPOpcode() ? 1 : 0).getNode();
8434 if (!Subtarget.hasP9Vector() && MMO->
getSize() <= 2)
8442 if (UI.getUse().get().getResNo() != 0)
8468 bool IsSingle =
Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT();
8471 EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64;
8472 if (
Op->isStrictFPOpcode()) {
8474 Chain =
Op.getOperand(0);
8486 const SDLoc &dl)
const {
8487 assert((
Op.getValueType() == MVT::f32 ||
8488 Op.getValueType() == MVT::f64) &&
8489 "Invalid floating point type as target of conversion");
8490 assert(Subtarget.hasFPCVT() &&
8491 "Int to FP conversions with direct moves require FPCVT");
8492 SDValue Src =
Op.getOperand(
Op->isStrictFPOpcode() ? 1 : 0);
8493 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
8515 for (
unsigned i = 1; i <
NumConcat; ++i)
8522 const SDLoc &dl)
const {
8524 unsigned Opc =
Op.getOpcode();
8528 "Unexpected conversion type");
8529 assert((
Op.getValueType() == MVT::v2f64 ||
Op.getValueType() == MVT::v4f32) &&
8530 "Supports conversions to v2f64/v4f32 only.");
8554 for (
int i = 1; i <=
SaveElts; i++)
8555 ShuffV[i * Stride - 1] = i - 1;
8565 if (Subtarget.hasP9Altivec())
8576 {Op.getOperand(0), Extend}, Flags);
8594 EVT InVT = Src.getValueType();
8596 if (
OutVT.isVector() &&
OutVT.isFloatingPoint() &&
8598 return LowerINT_TO_FPVector(
Op, DAG, dl);
8601 if (
Op.getValueType() == MVT::f128)
8602 return Subtarget.hasP9Vector() ?
Op :
SDValue();
8605 if (
Op.getValueType() != MVT::f32 &&
Op.getValueType() != MVT::f64)
8608 if (Src.getValueType() == MVT::i1) {
8620 if (Subtarget.hasDirectMove() && directMoveIsProfitable(
Op) &&
8621 Subtarget.
isPPC64() && Subtarget.hasFPCVT())
8622 return LowerINT_TO_FPDirectMove(
Op, DAG, dl);
8624 assert((IsSigned || Subtarget.hasFPCVT()) &&
8625 "UINT_TO_FP is supported only with FPCVT");
8627 if (Src.getValueType() == MVT::i64) {
8639 if (
Op.getValueType() == MVT::f32 &&
8640 !Subtarget.hasFPCVT() &&
8681 if (canReuseLoadAddress(
SINT, MVT::i64,
RLI, DAG)) {
8683 RLI.Alignment,
RLI.MMOFlags(),
RLI.AAInfo,
RLI.Ranges);
8684 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8685 }
else if (Subtarget.hasLFIWAX() &&
8693 Ops, MVT::i32, MMO);
8694 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8695 }
else if (Subtarget.hasFPCVT() &&
8703 Ops, MVT::i32, MMO);
8704 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8705 }
else if (((Subtarget.hasLFIWAX() &&
8707 (Subtarget.hasFPCVT() &&
8709 SINT.getOperand(0).getValueType() == MVT::i32) {
8722 "Expected an i32 store");
8738 Chain =
Bits.getValue(1);
8746 if (
Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8750 {Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
8758 assert(Src.getValueType() == MVT::i32 &&
8759 "Unhandled INT_TO_FP type in custom expander!");
8769 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
8772 if (!(
ReusingLoad = canReuseLoadAddress(Src, MVT::i32,
RLI, DAG))) {
8782 "Expected an i32 store");
8798 Chain =
Ld.getValue(1);
8800 spliceIntoChain(
RLI.ResChain,
Ld.getValue(1), DAG);
8803 "i32->FP without LFIWAX supported only on PPC64");
8818 MVT::f64, dl, Chain,
FIdx,
8820 Chain =
Ld.getValue(1);
8827 if (
Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8831 {Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
8862 EVT VT =
Op.getValueType();
8868 Chain =
MFFS.getValue(1);
8882 "Stack slot adjustment is valid only on big endian subtargets!");
8912 EVT VT =
Op.getValueType();
8916 VT ==
Op.getOperand(1).getValueType() &&
8941 EVT VT =
Op.getValueType();
8945 VT ==
Op.getOperand(1).getValueType() &&
8971 EVT VT =
Op.getValueType();
8974 VT ==
Op.getOperand(1).getValueType() &&
9001 EVT VT =
Op.getValueType();
9032 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
9038 if (Val == ((1LLU << (
SplatSize * 8)) - 1)) {
9075 DAG.
getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
9087 for (
unsigned i = 0; i != 16; ++i)
9108 EVT VecVT = V->getValueType(0);
9111 (
HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32));
9115 bool IsSplat =
true;
9116 bool IsLoad =
false;
9122 if (V->isConstant())
9124 for (
int i = 0, e = V->getNumOperands(); i < e; ++i) {
9125 if (V->getOperand(i).isUndef())
9129 if (V->getOperand(i).getOpcode() ==
ISD::LOAD ||
9131 V->getOperand(i).getOperand(0).getOpcode() ==
ISD::LOAD) ||
9133 V->getOperand(i).getOperand(0).getOpcode() ==
ISD::LOAD) ||
9135 V->getOperand(i).getOperand(0).getOpcode() ==
ISD::LOAD))
9139 if (V->getOperand(i) != Op0 ||
9140 (!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode())))
9143 return !(IsSplat && IsLoad);
9152 if ((
Op.getValueType() != MVT::f128) ||
9223 EVT Ty =
Op->getValueType(0);
9226 if ((Ty == MVT::v2f64 || Ty == MVT::v4f32 || Ty == MVT::v4i32) &&
9236 (
MemVT == Ty.getVectorElementType()))
9239 if (Ty == MVT::v2i64) {
9242 if (
MemVT == MVT::i32) {
9262 assert(
BVN &&
"Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
9266 unsigned SplatBitSize;
9277 Subtarget.hasPrefixInstrs()) {
9280 if ((
Op->getValueType(0) == MVT::v2f64) &&
9327 unsigned MemorySize =
LD->getMemoryVT().getScalarSizeInBits();
9328 unsigned ElementSize =
9331 assert(((ElementSize == 2 * MemorySize)
9335 "Unmatched element size and opcode!\n");
9360 Subtarget.hasLFIWAX()))
9369 Subtarget.isISA3_1() && ElementSize <= 16)
9374 Subtarget.hasVSX()) {
9382 LD->getMemoryVT(),
LD->getMemOperand());
9394 if (Subtarget.hasVSX() && Subtarget.
isPPC64() &&
9396 Subtarget.hasP8Vector()))
9408 if (SplatBits == 0) {
9422 if (Subtarget.hasPrefixInstrs() &&
SplatSize == 2)
9424 Op.getValueType(), DAG, dl);
9426 if (Subtarget.hasPrefixInstrs() &&
SplatSize == 4)
9431 if (Subtarget.hasP9Vector() &&
SplatSize == 1)
9436 int32_t
SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
9457 (
SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
9460 if (VT ==
Op.getValueType())
9469 if (
SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
9483 static const signed char SplatCsts[] = {
9484 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
9485 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
9488 for (
unsigned idx = 0; idx < std::size(
SplatCsts); ++idx) {
9500 static const unsigned IIDs[] = {
9501 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
9502 Intrinsic::ppc_altivec_vslw
9511 static const unsigned IIDs[] = {
9512 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
9513 Intrinsic::ppc_altivec_vsrw
9523 static const unsigned IIDs[] = {
9524 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
9525 Intrinsic::ppc_altivec_vrlw
9532 if (
SextVal == (
int)(((
unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
9538 if (
SextVal == (
int)(((
unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
9544 if (
SextVal == (
int)(((
unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
9559 unsigned OpNum = (
PFEntry >> 26) & 0x0F;
9577 if (
LHSID == (1*9+2)*9+3)
return LHS;
9578 assert(
LHSID == ((4*9+5)*9+6)*9+7 &&
"Illegal OP_COPY!");
9602 for (
unsigned i = 0; i != 16; ++i)
9606 for (
unsigned i = 0; i != 16; ++i)
9610 for (
unsigned i = 0; i != 16; ++i)
9614 for (
unsigned i = 0; i != 16; ++i)
9646 0, 15, 14, 13, 12, 11, 10, 9};
9648 1, 2, 3, 4, 5, 6, 7, 8};
9651 int OriginalOrder[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
9671 unsigned CurrentElement =
Mask[i];
9854 auto ShuffleMask =
SVN->getMask();
9879 unsigned SplatBitSize;
9895 if ((ShuffleMask[0] == 0 && ShuffleMask[8] == 8) &&
9896 (ShuffleMask[4] % 4 == 0 && ShuffleMask[12] % 4 == 0 &&
9897 ShuffleMask[4] > 15 && ShuffleMask[12] > 15))
9899 else if ((ShuffleMask[4] == 4 && ShuffleMask[12] == 12) &&
9900 (ShuffleMask[0] % 4 == 0 && ShuffleMask[8] % 4 == 0 &&
9901 ShuffleMask[0] > 15 && ShuffleMask[8] > 15))
9909 for (; SplatBitSize < 32; SplatBitSize <<= 1)
9924 assert(
Op.getValueType() == MVT::v1i128 &&
9925 "Only set v1i128 as custom, other type shouldn't reach here!");
9929 unsigned SHLAmt =
N1.getConstantOperandVal(0);
9931 std::array<int, 16>
Mask;
9932 std::iota(
Mask.begin(),
Mask.end(), 0);
9967 V1 =
Op.getOperand(0);
9968 V2 =
Op.getOperand(1);
9970 EVT VT =
Op.getValueType();
9981 if (
InputLoad && Subtarget.hasVSX() &&
V2.isUndef() &&
9993 "Unexpected size for permuted load on big endian target");
9996 "Splat of a value outside of the loaded memory");
10010 if (
LD->getValueType(0).getSizeInBits() == (
IsFourByte ? 32 : 64))
10026 Ops,
LD->getMemoryVT(),
LD->getMemOperand());
10028 if (
LdSplt.getValueType() !=
SVOp->getValueType(0))
10035 if (VT == MVT::v2i64 || VT == MVT::v2f64)
10038 if (Subtarget.hasP9Vector() &&
10057 if (Subtarget.hasPrefixInstrs()) {
10063 if (Subtarget.hasP9Altivec()) {
10072 if (Subtarget.hasVSX() &&
10085 if (Subtarget.hasVSX() &&
10098 if (Subtarget.hasP9Vector()) {
10118 if (Subtarget.hasVSX()) {
10139 if (
V2.isUndef()) {
10152 (Subtarget.hasP8Altivec() && (
10163 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
10173 (Subtarget.hasP8Altivec() && (
10188 unsigned EltNo = 8;
10189 for (
unsigned j = 0;
j != 4; ++
j) {
10220 unsigned Cost = (
PFEntry >> 30);
10240 if (
V2.isUndef())
V2 = V1;
10242 return LowerVPERM(
Op, DAG,
PermMask, VT, V1, V2);
10253 bool isPPC64 = Subtarget.
isPPC64();
10257 if (isLittleEndian)
10260 if (Subtarget.hasVSX() && Subtarget.hasP9Vector() &&
10262 LLVM_DEBUG(
dbgs() <<
"At least one of two input vectors are dead - using "
10263 "XXPERM instead\n");
10330 if (isLittleEndian)
10344 dl =
SDLoc(
V2->getOperand(0));
10345 V2 =
V2->getOperand(0)->getOperand(1);
10347 if (isPPC64 && ValType != MVT::v2f64)
10349 if (isPPC64 &&
V2.getValueType() != MVT::v2f64)
10358 dbgs() <<
"Emitting a XXPERM for the following shuffle:\n";
10360 dbgs() <<
"Emitting a VPERM for the following shuffle:\n";
10363 dbgs() <<
"With the following permute control vector:\n";
10382 unsigned IntrinsicID =
10386 switch (IntrinsicID) {
10390 case Intrinsic::ppc_altivec_vcmpbfp_p:
10394 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10398 case Intrinsic::ppc_altivec_vcmpequb_p:
10402 case Intrinsic::ppc_altivec_vcmpequh_p:
10406 case Intrinsic::ppc_altivec_vcmpequw_p:
10410 case Intrinsic::ppc_altivec_vcmpequd_p:
10411 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) {
10417 case Intrinsic::ppc_altivec_vcmpneb_p:
10418 case Intrinsic::ppc_altivec_vcmpneh_p:
10419 case Intrinsic::ppc_altivec_vcmpnew_p:
10420 case Intrinsic::ppc_altivec_vcmpnezb_p:
10421 case Intrinsic::ppc_altivec_vcmpnezh_p:
10422 case Intrinsic::ppc_altivec_vcmpnezw_p:
10423 if (Subtarget.hasP9Altivec()) {
10424 switch (IntrinsicID) {
10427 case Intrinsic::ppc_altivec_vcmpneb_p:
10430 case Intrinsic::ppc_altivec_vcmpneh_p:
10433 case Intrinsic::ppc_altivec_vcmpnew_p:
10436 case Intrinsic::ppc_altivec_vcmpnezb_p:
10439 case Intrinsic::ppc_altivec_vcmpnezh_p:
10442 case Intrinsic::ppc_altivec_vcmpnezw_p:
10450 case Intrinsic::ppc_altivec_vcmpgefp_p:
10454 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10458 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10462 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10466 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10470 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10471 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) {
10477 case Intrinsic::ppc_altivec_vcmpgtub_p:
10481 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10485 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10489 case Intrinsic::ppc_altivec_vcmpgtud_p:
10490 if (Subtarget.hasVSX() || Subtarget.hasP8Altivec()) {
10497 case Intrinsic::ppc_altivec_vcmpequq:
10498 case Intrinsic::ppc_altivec_vcmpgtsq:
10499 case Intrinsic::ppc_altivec_vcmpgtuq:
10500 if (!Subtarget.isISA3_1())
10502 switch (IntrinsicID) {
10505 case Intrinsic::ppc_altivec_vcmpequq:
10508 case Intrinsic::ppc_altivec_vcmpgtsq:
10511 case Intrinsic::ppc_altivec_vcmpgtuq:
10518 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
10519 case Intrinsic::ppc_vsx_xvcmpgedp_p:
10520 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
10521 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
10522 case Intrinsic::ppc_vsx_xvcmpgesp_p:
10523 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
10524 if (Subtarget.hasVSX()) {
10525 switch (IntrinsicID) {
10526 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
10529 case Intrinsic::ppc_vsx_xvcmpgedp_p:
10532 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
10535 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
10538 case Intrinsic::ppc_vsx_xvcmpgesp_p:
10541 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
10551 case Intrinsic::ppc_altivec_vcmpbfp:
10554 case Intrinsic::ppc_altivec_vcmpeqfp:
10557 case Intrinsic::ppc_altivec_vcmpequb:
10560 case Intrinsic::ppc_altivec_vcmpequh:
10563 case Intrinsic::ppc_altivec_vcmpequw:
10566 case Intrinsic::ppc_altivec_vcmpequd:
10567 if (Subtarget.hasP8Altivec())
10572 case Intrinsic::ppc_altivec_vcmpneb:
10573 case Intrinsic::ppc_altivec_vcmpneh:
10574 case Intrinsic::ppc_altivec_vcmpnew:
10575 case Intrinsic::ppc_altivec_vcmpnezb:
10576 case Intrinsic::ppc_altivec_vcmpnezh:
10577 case Intrinsic::ppc_altivec_vcmpnezw:
10578 if (Subtarget.hasP9Altivec())
10579 switch (IntrinsicID) {
10582 case Intrinsic::ppc_altivec_vcmpneb:
10585 case Intrinsic::ppc_altivec_vcmpneh:
10588 case Intrinsic::ppc_altivec_vcmpnew:
10591 case Intrinsic::ppc_altivec_vcmpnezb:
10594 case Intrinsic::ppc_altivec_vcmpnezh:
10597 case Intrinsic::ppc_altivec_vcmpnezw:
10604 case Intrinsic::ppc_altivec_vcmpgefp:
10607 case Intrinsic::ppc_altivec_vcmpgtfp:
10610 case Intrinsic::ppc_altivec_vcmpgtsb:
10613 case Intrinsic::ppc_altivec_vcmpgtsh:
10616 case Intrinsic::ppc_altivec_vcmpgtsw:
10619 case Intrinsic::ppc_altivec_vcmpgtsd:
10620 if (Subtarget.hasP8Altivec())
10625 case Intrinsic::ppc_altivec_vcmpgtub:
10628 case Intrinsic::ppc_altivec_vcmpgtuh:
10631 case Intrinsic::ppc_altivec_vcmpgtuw:
10634 case Intrinsic::ppc_altivec_vcmpgtud:
10635 if (Subtarget.hasP8Altivec())
10640 case Intrinsic::ppc_altivec_vcmpequq_p:
10641 case Intrinsic::ppc_altivec_vcmpgtsq_p:
10642 case Intrinsic::ppc_altivec_vcmpgtuq_p:
10643 if (!Subtarget.isISA3_1())
10645 switch (IntrinsicID) {
10648 case Intrinsic::ppc_altivec_vcmpequq_p:
10651 case Intrinsic::ppc_altivec_vcmpgtsq_p:
10654 case Intrinsic::ppc_altivec_vcmpgtuq_p:
10668 unsigned IntrinsicID =
10673 switch (IntrinsicID) {
10674 case Intrinsic::thread_pointer:
10680 case Intrinsic::ppc_mma_disassemble_acc: {
10681 if (Subtarget.isISAFuture()) {
10682 EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
10695 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0,
10697 RetOps.push_back(Extract);
10701 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1,
10703 RetOps.push_back(Extract);
10707 DAG.getConstant(Subtarget.isLittleEndian() ? 1 : 0,
10709 RetOps.push_back(Extract);
10713 DAG.getConstant(Subtarget.isLittleEndian() ? 0 : 1,
10715 RetOps.push_back(Extract);
10720 case Intrinsic::ppc_vsx_disassemble_pair: {
10723 if (IntrinsicID == Intrinsic::ppc_mma_disassemble_acc) {
10734 RetOps.push_back(Extract);
10739 case Intrinsic::ppc_mma_xxmfacc:
10740 case Intrinsic::ppc_mma_xxmtacc: {
10742 if (!Subtarget.isISAFuture())
10753 case Intrinsic::ppc_unpack_longdouble: {
10755 assert(
Idx && (
Idx->getSExtValue() == 0 ||
Idx->getSExtValue() == 1) &&
10756 "Argument of long double unpack must be 0 or 1!");
10759 Idx->getValueType(0)));
10762 case Intrinsic::ppc_compare_exp_lt:
10763 case Intrinsic::ppc_compare_exp_gt:
10764 case Intrinsic::ppc_compare_exp_eq:
10765 case Intrinsic::ppc_compare_exp_uo: {
10767 switch (IntrinsicID) {
10768 case Intrinsic::ppc_compare_exp_lt:
10771 case Intrinsic::ppc_compare_exp_gt:
10774 case Intrinsic::ppc_compare_exp_eq:
10777 case Intrinsic::ppc_compare_exp_uo:
10783 PPC::SELECT_CC_I4, dl, MVT::i32,
10784 {SDValue(DAG.getMachineNode(PPC::XSCMPEXPDP, dl, MVT::i32,
10785 Op.getOperand(1), Op.getOperand(2)),
10787 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32),
10788 DAG.getTargetConstant(Pred, dl, MVT::i32)}),
10791 case Intrinsic::ppc_test_data_class: {
10792 EVT OpVT =
Op.getOperand(1).getValueType();
10793 unsigned CmprOpc =
OpVT == MVT::f128 ? PPC::XSTSTDCQP
10794 : (
OpVT == MVT::f64 ? PPC::XSTSTDCDP
10798 PPC::SELECT_CC_I4, dl, MVT::i32,
10799 {SDValue(DAG.getMachineNode(CmprOpc, dl, MVT::i32, Op.getOperand(2),
10802 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32),
10803 DAG.getTargetConstant(PPC::PRED_EQ, dl, MVT::i32)}),
10806 case Intrinsic::ppc_fnmsub: {
10807 EVT VT =
Op.getOperand(1).getValueType();
10808 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128))
10814 Op.getOperand(2),
Op.getOperand(3));
10816 case Intrinsic::ppc_convert_f128_to_ppcf128:
10817 case Intrinsic::ppc_convert_ppcf128_to_f128: {
10819 ? RTLIB::CONVERT_PPCF128_F128
10820 : RTLIB::CONVERT_F128_PPCF128;
10822 std::pair<SDValue, SDValue>
Result =
10827 case Intrinsic::ppc_maxfe:
10828 case Intrinsic::ppc_maxfl:
10829 case Intrinsic::ppc_maxfs:
10830 case Intrinsic::ppc_minfe:
10831 case Intrinsic::ppc_minfl:
10832 case Intrinsic::ppc_minfs: {
10833 EVT VT =
Op.getValueType();
10836 [VT](
const SDUse &
Use) { return Use.getValueType() == VT; }) &&
10837 "ppc_[max|min]f[e|l|s] must have uniform type arguments");
10840 if (IntrinsicID == Intrinsic::ppc_minfe ||
10841 IntrinsicID == Intrinsic::ppc_minfl ||
10842 IntrinsicID == Intrinsic::ppc_minfs)
10864 Op.getOperand(1),
Op.getOperand(2),
10875 EVT VTs[] = {
Op.getOperand(2).getValueType(), MVT::Glue };
10924 case Intrinsic::ppc_cfence: {
10925 assert(
ArgStart == 1 &&
"llvm.ppc.cfence must carry a chain argument.");
10926 assert(Subtarget.
isPPC64() &&
"Only 64-bit is supported for now.");
10929 if (Ty == MVT::i128) {
10957 int VectorIndex = 0;
10970 "Expecting an atomic compare-and-swap here.");
10974 if (
MemVT.getSizeInBits() >= 32)
10991 for (
int i = 0, e =
AtomicNode->getNumOperands(); i <
e; i++)
11006 "Expect quadword atomic operations");
11008 unsigned Opc =
N->getOpcode();
11016 DAG.
getConstant(Intrinsic::ppc_atomic_load_i128, dl, MVT::i32)};
11017 for (
int I = 1,
E =
N->getNumOperands();
I <
E; ++
I)
11018 Ops.push_back(
N->getOperand(
I));
11020 Ops,
MemVT,
N->getMemOperand());
11037 DAG.
getConstant(Intrinsic::ppc_atomic_store_i128, dl, MVT::i32)};
11043 Ops.push_back(
ValLo);
11044 Ops.push_back(
ValHi);
11045 Ops.push_back(
N->getOperand(1));
11047 N->getMemOperand());
11069 EVT VT =
Op.getValueType();
11071 unsigned TestOp = VT == MVT::f128 ? PPC::XSTSTDCQP
11072 : VT == MVT::f64 ? PPC::XSTSTDCDP
11105 TargetOpcode::EXTRACT_SUBREG,
Dl, MVT::i1,
Rev,
11129 if (VT == MVT::f128) {
11134 }
else if (VT == MVT::f64) {
11147 }
else if (VT == MVT::f32) {
11182 TargetOpcode::EXTRACT_SUBREG,
Dl, MVT::i1,
11193 assert(Subtarget.hasP9Vector() &&
"Test data class requires Power9");
11220 "Should only be called for ISD::INSERT_VECTOR_ELT");
11224 EVT VT =
Op.getValueType();
11229 if (VT == MVT::v2f64 &&
C)
11232 if (Subtarget.hasP9Vector()) {
11241 if ((VT == MVT::v4f32) && (
V2.getValueType() == MVT::f32) &&
11252 if (Subtarget.isISA3_1()) {
11253 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.
isPPC64())
11257 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
11258 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
11268 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
11288 EVT VT =
Op.getValueType();
11290 if (VT != MVT::v256i1 && VT != MVT::v512i1)
11296 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) &&
11297 "Type unsupported without MMA");
11298 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) &&
11299 "Type unsupported without paired vector support");
11300 Align Alignment =
LN->getAlign();
11306 DAG.
getLoad(MVT::v16i8, dl, LoadChain, BasePtr,
11307 LN->getPointerInfo().getWithOffset(
Idx * 16),
11309 LN->getMemOperand()->getFlags(),
LN->getAAInfo());
11312 Loads.push_back(Load);
11316 std::reverse(Loads.begin(), Loads.end());
11344 "Type unsupported without MMA");
11345 assert((
StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) &&
11346 "Type unsupported without paired vector support");
11347 Align Alignment =
SN->getAlign();
11350 if (
StoreVT == MVT::v512i1) {
11351 if (Subtarget.isISAFuture()) {
11352 EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
11354 PPC::DMXXEXTFDMR512, dl,
ArrayRef(ReturnTypes, 2),
Op.getOperand(1));
11365 if (Subtarget.isISAFuture()) {
11376 SN->getPointerInfo().getWithOffset(
Idx * 16),
11378 SN->getMemOperand()->getFlags(),
SN->getAAInfo());
11381 Stores.push_back(Store);
11389 if (
Op.getValueType() == MVT::v4i32) {
11390 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
11406 LHS, RHS, DAG, dl, MVT::v4i32);
11409 LHS,
RHSSwap, Zero, DAG, dl, MVT::v4i32);
11414 }
else if (
Op.getValueType() == MVT::v16i8) {
11415 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
11420 LHS, RHS, DAG, dl, MVT::v8i16);
11425 LHS, RHS, DAG, dl, MVT::v8i16);
11433 for (
unsigned i = 0; i != 8; ++i) {
11434 if (isLittleEndian) {
11436 Ops[i*2+1] = 2*i+16;
11439 Ops[i*2+1] = 2*i+1+16;
11442 if (isLittleEndian)
11464 "Should only be called for ISD::FP_EXTEND");
11468 if (
Op.getValueType() != MVT::v2f64 ||
11469 Op.getOperand(0).getValueType() != MVT::v2f32)
11481 "Node should have 2 operands with second one being a constant!");
11516 LD->getMemoryVT(),
LD->getMemOperand());
11529 LD->getMemoryVT(),
LD->getMemOperand());
11540 switch (
Op.getOpcode()) {
11569 return LowerGET_DYNAMIC_AREA_OFFSET(
Op, DAG);
11595 case ISD::FSHL:
return LowerFunnelShift(
Op, DAG);
11596 case ISD::FSHR:
return LowerFunnelShift(
Op, DAG);
11608 return LowerFP_ROUND(
Op, DAG);
11621 return LowerINTRINSIC_VOID(
Op, DAG);
11623 return LowerBSWAP(
Op, DAG);
11625 return LowerATOMIC_CMP_SWAP(
Op, DAG);
11627 return LowerATOMIC_LOAD_STORE(
Op, DAG);
11629 return LowerIS_FPCLASS(
Op, DAG);
11637 switch (
N->getOpcode()) {
11639 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
11657 Intrinsic::loop_decrement)
11660 assert(
N->getValueType(0) == MVT::i1 &&
11661 "Unexpected result type for CTR decrement intrinsic");
11663 N->getValueType(0));
11674 case Intrinsic::ppc_pack_longdouble:
11676 N->getOperand(2),
N->getOperand(1)));
11678 case Intrinsic::ppc_maxfe:
11679 case Intrinsic::ppc_minfe:
11680 case Intrinsic::ppc_fnmsub:
11681 case Intrinsic::ppc_convert_f128_to_ppcf128:
11691 EVT VT =
N->getValueType(0);
11693 if (VT == MVT::i64) {
11706 if (
N->getOperand(
N->isStrictFPOpcode() ? 1 : 0).
getValueType() ==
11711 if (
N->isStrictFPOpcode())
11716 if (!
N->getValueType(0).isVector())
11743 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11745 return Builder.CreateCall(Func, {});
11768 return Builder.CreateCall(
11770 Builder.GetInsertBlock()->getParent()->getParent(),
11771 Intrinsic::ppc_cfence, {Inst->getType()}),
11796 assert(Subtarget.hasPartwordAtomics() &&
"Call this only with size >=4");
11801 assert(Subtarget.hasPartwordAtomics() &&
"Call this only with size >=4");
11833 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
11837 RegInfo.createVirtualRegister(
AtomicSize == 8 ? &PPC::G8RCRegClass
11838 : &PPC::GPRCRegClass);
11868 Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
11871 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11900 switch(
MI.getOpcode()) {
11904 return TII->isSignExtended(
MI.getOperand(1).getReg(),
11905 &
MI.getMF()->getRegInfo());
11929 case PPC::EXTSB8_32_64:
11930 case PPC::EXTSB8_rec:
11931 case PPC::EXTSB_rec:
11934 case PPC::EXTSH8_32_64:
11935 case PPC::EXTSH8_rec:
11936 case PPC::EXTSH_rec:
11938 case PPC::EXTSWSLI:
11939 case PPC::EXTSWSLI_32_64:
11940 case PPC::EXTSWSLI_32_64_rec:
11941 case PPC::EXTSWSLI_rec:
11942 case PPC::EXTSW_32:
11943 case PPC::EXTSW_32_64:
11944 case PPC::EXTSW_32_64_rec:
11945 case PPC::EXTSW_rec:
11948 case PPC::SRAWI_rec:
11949 case PPC::SRAW_rec:
11974 .
addReg(
MI.getOperand(3).getReg());
11979 if (Subtarget.hasPartwordAtomics())
11987 bool is64bit = Subtarget.
isPPC64();
11989 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
12008 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12011 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12017 isLittleEndian ?
Shift1Reg : RegInfo.createVirtualRegister(
GPRC);
12057 Ptr1Reg = RegInfo.createVirtualRegister(RC);
12071 if (!isLittleEndian)
12072 BuildMI(BB, dl,
TII->get(PPC::XORI), ShiftReg)
12115 Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
12182 Register DstReg =
MI.getOperand(0).getReg();
12184 assert(
TRI->isTypeLegalForClass(*RC, MVT::i32) &&
"Invalid destination!");
12190 "Invalid Pointer Size!");
12218 sinkMBB->transferSuccessorsAndUpdatePHIs(
MBB);
12254 BaseReg = Subtarget.
isPPC64() ? PPC::X1 : PPC::R1;
12256 BaseReg = Subtarget.
isPPC64() ? PPC::BP8 : PPC::BP;
12259 TII->get(Subtarget.
isPPC64() ? PPC::STD : PPC::STW))
12303 TII->get(PPC::PHI), DstReg)
12307 MI.eraseFromParent();
12322 "Invalid Pointer Size!");
12325 (
PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12328 unsigned FP = (
PVT == MVT::i64) ? PPC::X31 : PPC::R31;
12329 unsigned SP = (
PVT == MVT::i64) ? PPC::X1 : PPC::R1;
12339 const int64_t SPOffset = 2 *
PVT.getStoreSize();
12348 if (
PVT == MVT::i64) {
12360 if (
PVT == MVT::i64) {
12372 if (
PVT == MVT::i64) {
12384 if (
PVT == MVT::i64) {
12406 TII->get(
PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).
addReg(Tmp);
12409 MI.eraseFromParent();
12425 "Unexpected stack alignment");
12429 unsigned StackProbeSize =
12432 StackProbeSize &= ~(StackAlign - 1);
12433 return StackProbeSize ? StackProbeSize : StackAlign;
12445 const bool isPPC64 = Subtarget.
isPPC64();
12484 Register DstReg =
MI.getOperand(0).getReg();
12486 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
12497 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32;
12503 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
12504 : PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32;
12508 .
add(
MI.getOperand(2))
12509 .
add(
MI.getOperand(3));
12581 MRI.createVirtualRegister(isPPC64 ?
G8RC :
GPRC);
12583 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET),
12585 .
add(
MI.getOperand(2))
12586 .add(
MI.getOperand(3));
12594 TailMBB->transferSuccessorsAndUpdatePHIs(
MBB);
12598 MI.eraseFromParent();
12607 if (
MI.getOpcode() == TargetOpcode::STACKMAP ||
12608 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
12610 MI.getOpcode() == TargetOpcode::PATCHPOINT &&
12623 if (
MI.getOpcode() == PPC::EH_SjLj_SetJmp32 ||
12624 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) {
12626 }
else if (
MI.getOpcode() == PPC::EH_SjLj_LongJmp32 ||
12627 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) {
12641 if (
MI.getOpcode() == PPC::SELECT_CC_I4 ||
12642 MI.getOpcode() == PPC::SELECT_CC_I8 ||
MI.getOpcode() == PPC::SELECT_I4 ||
12643 MI.getOpcode() == PPC::SELECT_I8) {
12645 if (
MI.getOpcode() == PPC::SELECT_CC_I4 ||
12646 MI.getOpcode() == PPC::SELECT_CC_I8)
12647 Cond.push_back(
MI.getOperand(4));
12650 Cond.push_back(
MI.getOperand(1));
12653 TII->insertSelect(*BB,
MI, dl,
MI.getOperand(0).getReg(),
Cond,
12654 MI.getOperand(2).getReg(),
MI.getOperand(3).getReg());
12655 }
else if (
MI.getOpcode() == PPC::SELECT_CC_F4 ||
12656 MI.getOpcode() == PPC::SELECT_CC_F8 ||
12657 MI.getOpcode() == PPC::SELECT_CC_F16 ||
12658 MI.getOpcode() == PPC::SELECT_CC_VRRC ||
12659 MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
12660 MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
12661 MI.getOpcode() == PPC::SELECT_CC_VSRC ||
12662 MI.getOpcode() == PPC::SELECT_CC_SPE4 ||
12663 MI.getOpcode() == PPC::SELECT_CC_SPE ||
12664 MI.getOpcode() == PPC::SELECT_F4 ||
12665 MI.getOpcode() == PPC::SELECT_F8 ||
12666 MI.getOpcode() == PPC::SELECT_F16 ||
12667 MI.getOpcode() == PPC::SELECT_SPE ||
12668 MI.getOpcode() == PPC::SELECT_SPE4 ||
12669 MI.getOpcode() == PPC::SELECT_VRRC ||
12670 MI.getOpcode() == PPC::SELECT_VSFRC ||
12671 MI.getOpcode() == PPC::SELECT_VSSRC ||
12672 MI.getOpcode() == PPC::SELECT_VSRC) {
12693 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12699 if (
MI.getOpcode() == PPC::SELECT_I4 ||
MI.getOpcode() == PPC::SELECT_I8 ||
12700 MI.getOpcode() == PPC::SELECT_F4 ||
MI.getOpcode() == PPC::SELECT_F8 ||
12701 MI.getOpcode() == PPC::SELECT_F16 ||
12702 MI.getOpcode() == PPC::SELECT_SPE4 ||
12703 MI.getOpcode() == PPC::SELECT_SPE ||
12704 MI.getOpcode() == PPC::SELECT_VRRC ||
12705 MI.getOpcode() == PPC::SELECT_VSFRC ||
12706 MI.getOpcode() == PPC::SELECT_VSSRC ||
12707 MI.getOpcode() == PPC::SELECT_VSRC) {
12709 .
addReg(
MI.getOperand(1).getReg())
12715 .
addReg(
MI.getOperand(1).getReg())
12732 .
addReg(
MI.getOperand(3).getReg())
12734 .
addReg(
MI.getOperand(2).getReg())
12736 }
else if (
MI.getOpcode() == PPC::ReadTB) {
12758 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12772 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
12784 }
else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
12786 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
12788 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
12790 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
12793 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
12795 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
12797 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
12799 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
12802 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
12804 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
12806 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
12808 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
12811 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
12813 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
12815 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
12817 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
12820 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
12822 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
12824 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
12826 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
12829 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
12831 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
12833 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
12835 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
12838 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
12840 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
12842 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
12844 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
12847 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
12849 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
12851 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
12853 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
12856 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
12858 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
12860 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
12862 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
12865 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
12867 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
12869 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
12871 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
12874 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
12876 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
12878 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
12880 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
12882 else if (
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
12883 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
12884 (Subtarget.hasPartwordAtomics() &&
12885 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
12886 (Subtarget.hasPartwordAtomics() &&
12887 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
12888 bool is64bit =
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
12892 switch (
MI.getOpcode()) {
12895 case PPC::ATOMIC_CMP_SWAP_I8:
12898 assert(Subtarget.hasPartwordAtomics() &&
"No support partword atomics.");
12900 case PPC::ATOMIC_CMP_SWAP_I16:
12903 assert(Subtarget.hasPartwordAtomics() &&
"No support partword atomics.");
12905 case PPC::ATOMIC_CMP_SWAP_I32:
12909 case PPC::ATOMIC_CMP_SWAP_I64:
12918 Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
12931 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12975 }
else if (
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
12976 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
12980 bool is64bit = Subtarget.
isPPC64();
12982 bool is8bit =
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
12999 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
13003 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
13009 isLittleEndian ?
Shift1Reg : RegInfo.createVirtualRegister(
GPRC);
13021 Register TmpReg = RegInfo.createVirtualRegister(
GPRC);
13023 Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
13055 Ptr1Reg = RegInfo.createVirtualRegister(RC);
13070 if (!isLittleEndian)
13071 BuildMI(BB, dl,
TII->get(PPC::XORI), ShiftReg)
13151 }
else if (
MI.getOpcode() == PPC::FADDrtz) {
13161 Register MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
13176 auto MIB =
BuildMI(*BB,
MI, dl,
TII->get(PPC::FADD), Dest)
13184 }
else if (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
13185 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT ||
13186 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
13187 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8) {
13188 unsigned Opcode = (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
13189 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8)
13192 bool IsEQ = (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
13193 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8);
13196 Register Dest = RegInfo.createVirtualRegister(
13197 Opcode == PPC::ANDI_rec ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
13201 .
addReg(
MI.getOperand(1).getReg())
13204 MI.getOperand(0).getReg())
13206 }
else if (
MI.getOpcode() == PPC::TCHECK_RET) {
13209 Register CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
13212 MI.getOperand(0).getReg())
13214 }
else if (
MI.getOpcode() == PPC::TBEGIN_RET) {
13216 unsigned Imm =
MI.getOperand(1).getImm();
13219 MI.getOperand(0).getReg())
13221 }
else if (
MI.getOpcode() == PPC::SETRNDi) {
13240 unsigned Mode =
MI.getOperand(1).getImm();
13241 BuildMI(*BB,
MI, dl,
TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0))
13245 BuildMI(*BB,
MI, dl,
TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0))
13248 }
else if (
MI.getOpcode() == PPC::SETRND) {
13257 if (Subtarget.hasDirectMove()) {
13258 BuildMI(*BB,
MI, dl,
TII->get(TargetOpcode::COPY), DestReg)
13265 if (RC == &PPC::F8RCRegClass) {
13267 assert((RegInfo.getRegClass(DestReg) == &PPC::G8RCRegClass) &&
13268 "Unsupported RegClass.");
13274 assert((RegInfo.getRegClass(SrcReg) == &PPC::G8RCRegClass) &&
13275 (RegInfo.getRegClass(DestReg) == &PPC::F8RCRegClass) &&
13276 "Unsupported RegClass.");
13357 }
else if (
MI.getOpcode() == PPC::SETFLM) {
13374 }
else if (
MI.getOpcode() == PPC::PROBED_ALLOCA_32 ||
13375 MI.getOpcode() == PPC::PROBED_ALLOCA_64) {
13377 }
else if (
MI.getOpcode() == PPC::SPLIT_QUADWORD) {
13384 .
addUse(Src, 0, PPC::sub_gp8_x1);
13387 .
addUse(Src, 0, PPC::sub_gp8_x0);
13388 }
else if (
MI.getOpcode() == PPC::LQX_PSEUDO ||
13389 MI.getOpcode() == PPC::STQX_PSEUDO) {
13395 F->getRegInfo().createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
13401 MI.getOpcode() == PPC::LQX_PSEUDO ?
TII->get(PPC::LQ)
13402 :
TII->get(PPC::STQ))
13410 MI.eraseFromParent();
13432 EVT VT =
Op.getValueType();
13435 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())))
13459PPCTargetLowering::getSqrtResultForDenormInput(
SDValue Op,
13462 EVT VT =
Op.getValueType();
13463 if (VT != MVT::f64 &&
13464 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))
13475 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
13476 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
13477 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
13478 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
13494 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
13495 (VT == MVT::f64 && Subtarget.hasFRE()) ||
13496 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
13497 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
13505unsigned PPCTargetLowering::combineRepeatedFPDivisors()
const {
13533 Base = Loc.getOperand(0);
13543 unsigned Bytes,
int Dist,
13557 if (FS !=
BFS || FS != (
int)Bytes)
return false;
13583 unsigned Bytes,
int Dist,
13586 EVT VT = LS->getMemoryVT();
13587 SDValue Loc = LS->getBasePtr();
13594 default:
return false;
13595 case Intrinsic::ppc_altivec_lvx:
13596 case Intrinsic::ppc_altivec_lvxl:
13597 case Intrinsic::ppc_vsx_lxvw4x:
13598 case Intrinsic::ppc_vsx_lxvw4x_be:
13601 case Intrinsic::ppc_vsx_lxvd2x:
13602 case Intrinsic::ppc_vsx_lxvd2x_be:
13605 case Intrinsic::ppc_altivec_lvebx:
13608 case Intrinsic::ppc_altivec_lvehx:
13611 case Intrinsic::ppc_altivec_lvewx:
13622 default:
return false;
13623 case Intrinsic::ppc_altivec_stvx:
13624 case Intrinsic::ppc_altivec_stvxl:
13625 case Intrinsic::ppc_vsx_stxvw4x:
13628 case Intrinsic::ppc_vsx_stxvd2x:
13631 case Intrinsic::ppc_vsx_stxvw4x_be:
13634 case Intrinsic::ppc_vsx_stxvd2x_be:
13637 case Intrinsic::ppc_altivec_stvebx:
13640 case Intrinsic::ppc_altivec_stvehx:
13643 case Intrinsic::ppc_altivec_stvewx:
13660 SDValue Chain = LD->getChain();
13661 EVT VT = LD->getMemoryVT();
13670 while (!Queue.empty()) {
13679 if (!Visited.count(
ChainLD->getChain().getNode()))
13680 Queue.push_back(
ChainLD->getChain().getNode());
13683 if (!Visited.count(O.getNode()))
13684 Queue.push_back(O.getNode());
13698 Queue.push_back(
I);
13700 while (!Queue.empty()) {
13702 if (!Visited.insert(
LoadRoot).second)
13714 Queue.push_back(U);
13758 DAGCombinerInfo &
DCI)
const {
13766 if (!
DCI.isAfterLegalizeDAG())
13776 auto OpSize =
N->getOperand(0).getValueSizeInBits();
13798 DAGCombinerInfo &
DCI)
const {
13802 assert(Subtarget.useCRBits() &&
"Expecting to be tracking CR bits");
13813 N->getValueType(0) != MVT::i1)
13816 if (
N->getOperand(0).getValueType() != MVT::i32 &&
13817 N->getOperand(0).getValueType() != MVT::i64)
13827 unsigned OpBits =
N->getOperand(0).getValueSizeInBits();
13838 return (
N->getOpcode() ==
ISD::SETCC ? ConvertSETCCToSubtract(
N,
DCI)
13861 if (
N->getOperand(0).getOpcode() !=
ISD::AND &&
13862 N->getOperand(0).getOpcode() !=
ISD::OR &&
13863 N->getOperand(0).getOpcode() !=
ISD::XOR &&
13873 N->getOperand(1).getOpcode() !=
ISD::AND &&
13874 N->getOperand(1).getOpcode() !=
ISD::OR &&
13875 N->getOperand(1).getOpcode() !=
ISD::XOR &&
13888 for (
unsigned i = 0; i < 2; ++i) {
13892 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
13894 Inputs.push_back(
N->getOperand(i));
13896 BinOps.push_back(
N->getOperand(i));
13904 while (!
BinOps.empty()) {
13907 if (!Visited.insert(BinOp.
getNode()).second)
13946 for (
unsigned i = 0,
ie = Inputs.size(); i !=
ie; ++i) {
13970 for (
unsigned i = 0,
ie =
PromOps.size(); i !=
ie; ++i) {
13992 for (
unsigned i = 0,
ie = Inputs.size(); i !=
ie; ++i) {
14019 PromOp.getOperand(0).getValueType() != MVT::i1) {
14034 switch (
PromOp.getOpcode()) {
14035 default:
C = 0;
break;
14041 PromOp.getOperand(
C).getValueType() != MVT::i1) ||
14043 PromOp.getOperand(
C+1).getValueType() != MVT::i1)) {
14053 PromOp.getNode()->op_end());
14056 for (
unsigned i = 0; i < 2; ++i)
14066 return N->getOperand(0);
14074 DAGCombinerInfo &
DCI)
const {
14092 if (
N->getValueType(0) != MVT::i32 &&
14093 N->getValueType(0) != MVT::i64)
14096 if (!((
N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
14097 (
N->getOperand(0).getValueType() == MVT::i32 && Subtarget.
isPPC64())))
14100 if (
N->getOperand(0).getOpcode() !=
ISD::AND &&
14101 N->getOperand(0).getOpcode() !=
ISD::OR &&
14102 N->getOperand(0).getOpcode() !=
ISD::XOR &&
14113 while (!
BinOps.empty()) {
14116 if (!Visited.insert(BinOp.
getNode()).second)
14152 for (
unsigned i = 0,
ie = Inputs.size(); i !=
ie; ++i) {
14177 for (
unsigned i = 0,
ie =
PromOps.size(); i !=
ie; ++i) {
14199 unsigned PromBits =
N->getOperand(0).getValueSizeInBits();
14204 for (
unsigned i = 0,
ie = Inputs.size(); i !=
ie; ++i) {
14209 Inputs[i].getOperand(0).getValueSizeInBits();
14227 for (
unsigned i = 0,
ie = Inputs.size(); i !=
ie; ++i) {
14261 switch (
PromOp.getOpcode()) {
14262 default:
C = 0;
break;
14268 PromOp.getOperand(
C).getValueType() !=
N->getValueType(0)) ||
14270 PromOp.getOperand(
C+1).getValueType() !=
N->getValueType(0))) {
14284 PromOp.getOperand(0).getValueType() !=
N->getValueType(0)) ||
14286 PromOp.getOperand(1).getValueType() !=
N->getValueType(0))) {
14293 PromOp.getNode()->op_end());
14296 for (
unsigned i = 0; i < 2; ++i) {
14328 return N->getOperand(0);
14336 dl,
N->getValueType(0)));
14339 "Invalid extension type");
14350 DAGCombinerInfo &
DCI)
const {
14352 "Should be called with a SETCC node");
14370 EVT VT =
N->getValueType(0);
14371 EVT OpVT = LHS.getValueType();
14377 return DAGCombineTruncBoolExt(
N,
DCI);
14384 Op.getValueType() == MVT::f64;
14396combineElementTruncationToVectorTruncation(
SDNode *
N,
14397 DAGCombinerInfo &
DCI)
const {
14399 "Should be called with a BUILD_VECTOR node");
14406 "The input operand must be an fp-to-int conversion.");
14415 bool IsSplat =
true;
14421 for (
int i = 0, e =
N->getNumOperands(); i <
e; ++i) {
14445 for (
int i = 0, e =
N->getNumOperands(); i <
e; ++i) {
14446 SDValue In =
N->getOperand(i).getOperand(0);
14456 Ops.push_back(Trunc);
14484 "Should be called with a BUILD_VECTOR node");
14489 if (!
N->getValueType(0).getVectorElementType().isByteSized())
14494 unsigned ElemSize =
N->getValueType(0).getScalarType().getStoreSize();
14506 N->getNumOperands() == 1)
14514 for (
int i = 1, e =
N->getNumOperands(); i < e; ++i) {
14547 "The loads cannot be both consecutive and reverse consecutive.");
14564 for (
int i =
N->getNumOperands() - 1; i >= 0; i--)
14568 DAG.
getUNDEF(
N->getValueType(0)), Ops);
14585 unsigned NumElems = Input.getValueType().getVectorNumElements();
14591 for (
unsigned i = 0; i <
N->getNumOperands(); i++) {
14595 ShuffleMask[(
CorrectElems & 0xF0) >> 4] = (Elems & 0xF0) >> 4;
14597 Elems = Elems >> 8;
14602 DAG.
getUNDEF(Input.getValueType()), ShuffleMask);
14604 EVT VT =
N->getValueType(0);
14608 Input.getValueType().getVectorElementType(),
14662 if (Input && Input != Extract.
getOperand(0))
14668 Elems = Elems << 8;
14677 for (
unsigned i = 0; i <
N->getNumOperands(); i++) {
14686 int InputSize = Input.getValueType().getScalarSizeInBits();
14687 int OutputSize =
N->getValueType(0).getScalarSizeInBits();
14721 if (
N->getValueType(0) != MVT::v1i128)
14731 EVT MemoryType = LD->getMemoryVT();
14735 bool ValidLDType = MemoryType == MVT::i8 || MemoryType == MVT::i16 ||
14736 MemoryType == MVT::i32 || MemoryType == MVT::i64;
14745 LD->getChain(), LD->getBasePtr(),
14749 DAG.
getVTList(MVT::v1i128, MVT::Other),
14750 LoadOps, MemoryType, LD->getMemOperand());
14754 DAGCombinerInfo &
DCI)
const {
14756 "Should be called with a BUILD_VECTOR node");
14761 if (!Subtarget.hasVSX())
14784 if (Subtarget.hasP9Altivec() && !
DCI.isBeforeLegalize()) {
14793 if (Subtarget.isISA3_1()) {
14799 if (
N->getValueType(0) != MVT::v2f64)
14810 if (
FirstInput.getOpcode() !=
N->getOperand(1).getOpcode())
14823 if (
Ext1.getOperand(0).getValueType() != MVT::v4i32 ||
14824 Ext1.getOperand(0) !=
Ext2.getOperand(0))
14840 return DAG.
getNode(NodeType, dl, MVT::v2f64,
14845 DAGCombinerInfo &
DCI)
const {
14848 "Need an int -> FP conversion node here");
14859 if (
Op.getValueType() != MVT::f32 &&
Op.getValueType() != MVT::f64)
14861 if (!
Op.getOperand(0).getValueType().isSimple())
14863 if (
Op.getOperand(0).getValueType().getSimpleVT() <=
MVT(MVT::i1) ||
14864 Op.getOperand(0).getValueType().getSimpleVT() >
MVT(MVT::i64))
14871 if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() &&
SubWordLoad) {
14884 Ops, MVT::i8,
LDN->getMemOperand());
14900 if (
Op.getOperand(0).getValueType() == MVT::i32)
14904 "UINT_TO_FP is supported only with FPCVT");
14908 unsigned FCFOp = (Subtarget.hasFPCVT() &&
Op.getValueType() == MVT::f32)
14913 MVT FCFTy = (Subtarget.hasFPCVT() &&
Op.getValueType() == MVT::f32)
14920 Subtarget.hasFPCVT()) ||
14922 SDValue Src =
Op.getOperand(0).getOperand(0);
14923 if (Src.getValueType() == MVT::f32) {
14925 DCI.AddToWorklist(Src.getNode());
14926 }
else if (Src.getValueType() != MVT::f64) {
14938 if (
Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
14941 DCI.AddToWorklist(
FP.getNode());
14956 if (
DCI.isBeforeLegalizeOps())
14965 switch (
N->getOpcode()) {
14970 Chain = LD->getChain();
14971 Base = LD->getBasePtr();
14972 MMO = LD->getMemOperand();
14982 Chain =
Intrin->getChain();
14986 MMO =
Intrin->getMemOperand();
14991 MVT VecTy =
N->getValueType(0).getSimpleVT();
14998 DCI.AddToWorklist(Load.getNode());
14999 Chain = Load.getValue(1);
15005 if (VecTy != MVT::v2f64) {
15007 DCI.AddToWorklist(
N.getNode());
15022 if (
DCI.isBeforeLegalizeOps())
15032 switch (
N->getOpcode()) {
15037 Chain = ST->getChain();
15038 Base = ST->getBasePtr();
15039 MMO = ST->getMemOperand();
15050 Chain =
Intrin->getChain();
15053 MMO =
Intrin->getMemOperand();
15060 MVT VecTy = Src.getValueType().getSimpleVT();
15063 if (VecTy != MVT::v2f64) {
15065 DCI.AddToWorklist(Src.getNode());
15069 DAG.
getVTList(MVT::v2f64, MVT::Other), Chain, Src);
15076 DCI.AddToWorklist(Store.getNode());
15082 DAGCombinerInfo &
DCI)
const {
15085 unsigned Opcode =
N->getOperand(1).getOpcode();
15087 bool Strict =
N->getOperand(1)->isStrictFPOpcode();
15091 &&
"Not a FP_TO_INT Instruction!");
15094 EVT Op1VT =
N->getOperand(1).getValueType();
15103 (Subtarget.hasP9Vector() && (
Op1VT == MVT::i16 ||
Op1VT == MVT::i8)));
15106 if (
ResVT == MVT::ppcf128 || (
ResVT == MVT::f128 && !Subtarget.hasP9Vector()))
15109 if ((
Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) ||
15116 unsigned ByteSize =
Op1VT.getScalarSizeInBits() / 8;
15133 for (
int i = 1, e = Mask.size(); i < e; i++) {
15150 FirstOp =
Op.getOperand(i);
15157 if (
Op.getOperand(i) != FirstOp && !
Op.getOperand(i).isUndef())
15167 Op =
Op.getOperand(0);
15186 for (
int i = 0, e =
ShuffV.size(); i < e; i++) {
15204 "Expecting a SCALAR_TO_VECTOR here");
15217 "Cannot produce a permuted scalar_to_vector for one element vector");
15246 int NumElts = LHS.getValueType().getVectorNumElements();
15256 if (!Subtarget.hasDirectMove())
15283 (
SToVLHS.getValueType().getScalarSizeInBits() !=
15284 SToVRHS.getValueType().getScalarSizeInBits()))
15288 :
SToVRHS.getValueType().getVectorNumElements();
15296 LHS.getValueType().getScalarSizeInBits()
15297 :
SToVRHS.getValueType().getScalarSizeInBits() /
15298 RHS.getValueType().getScalarSizeInBits();
15305 int HalfVec = LHS.getValueType().getVectorNumElements() / 2;
15314 if (!IsLittleEndian &&
SToVLHS.getValueType().getScalarSizeInBits() >= 64)
15319 if (
SToVLHS.getValueType() != LHS.getValueType())
15324 if (!IsLittleEndian &&
SToVRHS.getValueType().getScalarSizeInBits() >= 64)
15329 if (
SToVRHS.getValueType() != RHS.getValueType())
15366 if (IsLittleEndian) {
15369 if (Mask[0] < NumElts)
15370 for (
int i = 1, e =
Mask.size(); i <
e; i += 2) {
15378 for (
int i = 0, e =
Mask.size(); i <
e; i += 2) {
15386 if (Mask[0] < NumElts)
15387 for (
int i = 0, e =
Mask.size(); i <
e; i += 2) {
15395 for (
int i = 1, e =
Mask.size(); i <
e; i += 2) {
15408 if (IsLittleEndian)
15417 DAGCombinerInfo &
DCI)
const {
15419 "Not a reverse memop pattern!");
15424 auto I =
Mask.rbegin();
15425 auto E =
Mask.rend();
15427 for (;
I !=
E; ++
I) {
15436 EVT VT =
SVN->getValueType(0);
15444 if (!Subtarget.hasP9Vector())
15470 if (!
SVN->hasOneUse())
15485 unsigned IntrinsicID =
15487 if (IntrinsicID == Intrinsic::ppc_stdcx)
15489 else if (IntrinsicID == Intrinsic::ppc_stwcx)
15491 else if (IntrinsicID == Intrinsic::ppc_sthcx)
15493 else if (IntrinsicID == Intrinsic::ppc_stbcx)
15504 switch (
N->getOpcode()) {
15507 return combineADD(
N,
DCI);
15533 return combineSHL(
N,
DCI);
15535 return combineSRA(
N,
DCI);
15537 return combineSRL(
N,
DCI);
15539 return combineMUL(
N,
DCI);
15542 return combineFMALike(
N,
DCI);
15545 return N->getOperand(0);
15549 return N->getOperand(0);
15555 return N->getOperand(0);
15561 return DAGCombineExtBoolTrunc(
N,
DCI);
15563 return combineTRUNCATE(
N,
DCI);
15569 return DAGCombineTruncBoolExt(
N,
DCI);
15572 return combineFPToIntToFP(
N,
DCI);
15581 EVT Op1VT =
N->getOperand(1).getValueType();
15582 unsigned Opcode =
N->getOperand(1).getOpcode();
15600 N->getOperand(1).getNode()->hasOneUse() &&
15602 (Subtarget.hasLDBRX() && Subtarget.
isPPC64() &&
Op1VT == MVT::i64))) {
15607 if (
mVT.isExtended() ||
mVT.getSizeInBits() < 16)
15612 if (
BSwapOp.getValueType() == MVT::i16)
15618 int Shift =
Op1VT.getSizeInBits() -
mVT.getSizeInBits();
15622 if (
Op1VT == MVT::i64)
15637 if (Subtarget.
isPPC64() && !
DCI.isBeforeLegalize() &&
15642 MemVT.getSizeInBits());
15656 if (
Op1VT.isSimple()) {
15667 EVT VT = LD->getValueType(0);
15687 if (VT != MVT::i64)
15702 if (!LD->hasNUsesOfValue(2, 0))
15705 auto UI = LD->use_begin();
15706 while (UI.getUse().getResNo() != 0) ++UI;
15708 while (UI.getUse().getResNo() != 0) ++UI;
15709 SDNode *RightShift = *UI;
15717 if (RightShift->getOpcode() !=
ISD::SRL ||
15719 RightShift->getConstantOperandVal(1) != 32 ||
15720 !RightShift->hasOneUse())
15725 Trunc2->getValueType(0) != MVT::i32 ||
15733 Bitcast->getValueType(0) != MVT::f32)
15736 Bitcast2->getValueType(0) != MVT::f32)
15745 SDValue BasePtr = LD->getBasePtr();
15746 if (LD->isIndexed()) {
15748 "Non-pre-inc AM on PPC?");
15757 LD->getPointerInfo(), LD->getAlign(),
15758 MMOFlags, LD->getAAInfo());
15764 LD->getPointerInfo().getWithOffset(4),
15767 if (LD->isIndexed()) {
15787 if (LD->isUnindexed() && VT.
isVector() &&
15790 !Subtarget.hasP8Vector() &&
15791 (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
15792 VT == MVT::v4f32))) &&
15795 SDValue Chain = LD->getChain();
15825 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr
15826 : Intrinsic::ppc_altivec_lvsl;
15827 IntrLD = Intrinsic::ppc_altivec_lvx;
15828 IntrPerm = Intrinsic::ppc_altivec_vperm;
15843 -(int64_t)
MemVT.getStoreSize()+1,
15844 2*
MemVT.getStoreSize()-1);
15878 1, 2*
MemVT.getStoreSize()-1);
15894 if (isLittleEndian)
15902 Perm = Subtarget.hasAltivec()
15920 : Intrinsic::ppc_altivec_lvsl);
15921 if (IID ==
Intr &&
N->getOperand(1)->getOpcode() ==
ISD::ADD) {
15928 .zext(
Add.getScalarValueSizeInBits()))) {
15929 SDNode *BasePtr =
Add->getOperand(0).getNode();
15930 for (
SDNode *U : BasePtr->uses()) {
15943 SDNode *BasePtr =
Add->getOperand(0).getNode();
15944 for (
SDNode *U : BasePtr->uses()) {
15966 if (!
DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() &&
15967 (IID == Intrinsic::ppc_altivec_vmaxsw ||
15968 IID == Intrinsic::ppc_altivec_vmaxsh ||
15969 IID == Intrinsic::ppc_altivec_vmaxsb)) {
15985 V2.getOperand(1) == V1) {
16003 case Intrinsic::ppc_altivec_vsum4sbs:
16004 case Intrinsic::ppc_altivec_vsum4shs:
16005 case Intrinsic::ppc_altivec_vsum4ubs: {
16013 unsigned SplatBitSize;
16024 case Intrinsic::ppc_vsx_lxvw4x:
16025 case Intrinsic::ppc_vsx_lxvd2x:
16040 case Intrinsic::ppc_vsx_stxvw4x:
16041 case Intrinsic::ppc_vsx_stxvd2x:
16051 Subtarget.
isPPC64() &&
N->getValueType(0) == MVT::i64;
16053 N->getOperand(0).hasOneUse();
16055 (
N->getValueType(0) == MVT::i32 ||
N->getValueType(0) == MVT::i16 ||
16067 DAG.
getVTList(
N->getValueType(0) == MVT::i64 ?
16068 MVT::i64 : MVT::i32, MVT::Other),
16069 Ops, LD->getMemoryVT(), LD->getMemOperand());
16073 if (
N->getValueType(0) == MVT::i16)
16095 if (!LD->isSimple())
16097 SDValue BasePtr = LD->getBasePtr();
16099 LD->getPointerInfo(), LD->getAlign());
16104 LD->getMemOperand(), 4, 4);
16114 Hi.getOperand(0).getValue(1),
Lo.getOperand(0).getValue(1));
16123 if (!
N->getOperand(0).hasOneUse() &&
16124 !
N->getOperand(1).hasOneUse() &&
16125 !
N->getOperand(2).hasOneUse()) {
16134 UI->getOperand(1) ==
N->getOperand(1) &&
16135 UI->getOperand(2) ==
N->getOperand(2) &&
16136 UI->getOperand(0) ==
N->getOperand(0)) {
16191 unsigned Val =
RHSAPInt.getZExtValue();
16195 if (Val != 0 && Val != 1) {
16197 return N->getOperand(0);
16200 N->getOperand(0),
N->getOperand(4));
16225 DAG.
getVTList(MVT::i32, MVT::Other, MVT::Glue), Ops,
16226 MemNode->getMemoryVT(), MemNode->getMemOperand());
16230 if (
N->getOperand(0) == LHS.getValue(1))
16235 for (
int i = 0, e =
InTF.getNumOperands(); i < e; i++)
16236 if (
InTF.getOperand(i) != LHS.getValue(1))
16249 assert(
isDot &&
"Can't compare against a vector result!");
16261 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
16290 return DAGCombineBuildVector(
N,
DCI);
16301 EVT VT =
N->getValueType(0);
16302 if (VT == MVT::i64 && !Subtarget.
isPPC64())
16304 if ((VT != MVT::i32 && VT != MVT::i64) ||
16316 Created.push_back(
Op.getNode());
16320 Created.push_back(
Op.getNode());
16334 unsigned Depth)
const {
16336 switch (
Op.getOpcode()) {
16341 Known.
Zero = 0xFFFF0000;
16347 case Intrinsic::ppc_altivec_vcmpbfp_p:
16348 case Intrinsic::ppc_altivec_vcmpeqfp_p:
16349 case Intrinsic::ppc_altivec_vcmpequb_p:
16350 case Intrinsic::ppc_altivec_vcmpequh_p:
16351 case Intrinsic::ppc_altivec_vcmpequw_p:
16352 case Intrinsic::ppc_altivec_vcmpequd_p:
16353 case Intrinsic::ppc_altivec_vcmpequq_p:
16354 case Intrinsic::ppc_altivec_vcmpgefp_p:
16355 case Intrinsic::ppc_altivec_vcmpgtfp_p:
16356 case Intrinsic::ppc_altivec_vcmpgtsb_p:
16357 case Intrinsic::ppc_altivec_vcmpgtsh_p:
16358 case Intrinsic::ppc_altivec_vcmpgtsw_p:
16359 case Intrinsic::ppc_altivec_vcmpgtsd_p:
16360 case Intrinsic::ppc_altivec_vcmpgtsq_p:
16361 case Intrinsic::ppc_altivec_vcmpgtub_p:
16362 case Intrinsic::ppc_altivec_vcmpgtuh_p:
16363 case Intrinsic::ppc_altivec_vcmpgtuw_p:
16364 case Intrinsic::ppc_altivec_vcmpgtud_p:
16365 case Intrinsic::ppc_altivec_vcmpgtuq_p:
16375 case Intrinsic::ppc_load2r:
16377 Known.
Zero = 0xFFFF0000;
16407 if (
ML->getLoopDepth() > 1 &&
ML->getSubLoops().empty())
16416 for (
auto I =
ML->block_begin(), IE =
ML->block_end();
I != IE; ++
I)
16418 LoopSize +=
TII->getInstSizeInBytes(J);
16423 if (LoopSize > 16 && LoopSize <= 32)
16437 if (Constraint.
size() == 1) {
16438 switch (Constraint[0]) {
16456 }
else if (Constraint ==
"wc") {
16458 }
else if (Constraint ==
"wa" || Constraint ==
"wd" ||
16459 Constraint ==
"wf" || Constraint ==
"ws" ||
16460 Constraint ==
"wi" || Constraint ==
"ww") {
16473 Value *CallOperandVal =
info.CallOperandVal;
16476 if (!CallOperandVal)
16486 type->isVectorTy())
16500 if (type->isIntegerTy())
16504 if (type->isFloatTy())
16508 if (type->isDoubleTy())
16512 if (type->isVectorTy())
16525std::pair<unsigned, const TargetRegisterClass *>
16529 if (Constraint.
size() == 1) {
16531 switch (Constraint[0]) {
16533 if (VT == MVT::i64 && Subtarget.
isPPC64())
16534 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
16535 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
16537 if (VT == MVT::i64 && Subtarget.
isPPC64())
16538 return std::make_pair(0U, &PPC::G8RCRegClass);
16539 return std::make_pair(0U, &PPC::GPRCRegClass);
16545 if (Subtarget.hasSPE()) {
16546 if (VT == MVT::f32 || VT == MVT::i32)
16547 return std::make_pair(0U, &PPC::GPRCRegClass);
16548 if (VT == MVT::f64 || VT == MVT::i64)
16549 return std::make_pair(0U, &PPC::SPERCRegClass);
16551 if (VT == MVT::f32 || VT == MVT::i32)
16552 return std::make_pair(0U, &PPC::F4RCRegClass);
16553 if (VT == MVT::f64 || VT == MVT::i64)
16554 return std::make_pair(0U, &PPC::F8RCRegClass);
16558 if (Subtarget.hasAltivec() && VT.
isVector())
16559 return std::make_pair(0U, &PPC::VRRCRegClass);
16560 else if (Subtarget.hasVSX())
16562 return std::make_pair(0U, &PPC::VFRCRegClass);
16565 return std::make_pair(0U, &PPC::CRRCRegClass);
16567 }
else if (Constraint ==
"wc" && Subtarget.useCRBits()) {
16569 return std::make_pair(0U, &PPC::CRBITRCRegClass);
16570 }
else if ((Constraint ==
"wa" || Constraint ==
"wd" ||
16571 Constraint ==
"wf" || Constraint ==
"wi") &&
16572 Subtarget.hasVSX()) {
16576 return std::make_pair(0U, &PPC::VSRCRegClass);
16577 if (VT == MVT::f32 && Subtarget.hasP8Vector())
16578 return std::make_pair(0U, &PPC::VSSRCRegClass);
16579 return std::make_pair(0U, &PPC::VSFRCRegClass);
16580 }
else if ((Constraint ==
"ws" || Constraint ==
"ww") && Subtarget.hasVSX()) {
16581 if (VT == MVT::f32 && Subtarget.hasP8Vector())
16582 return std::make_pair(0U, &PPC::VSSRCRegClass);
16584 return std::make_pair(0U, &PPC::VSFRCRegClass);
16585 }
else if (Constraint ==
"lr") {
16586 if (VT == MVT::i64)
16587 return std::make_pair(0U, &PPC::LR8RCRegClass);
16589 return std::make_pair(0U, &PPC::LRRCRegClass);
16594 if (Constraint[0] ==
'{' && Constraint[Constraint.
size() - 1] ==
'}') {
16598 if (Constraint.
size() > 3 && Constraint[1] ==
'v' && Constraint[2] ==
's') {
16601 "Attempted to access a vsr out of range");
16603 return std::make_pair(PPC::VSL0 +
VSNum, &PPC::VSRCRegClass);
16604 return std::make_pair(PPC::V0 +
VSNum - 32, &PPC::VSRCRegClass);
16609 if (Constraint.
size() > 3 && Constraint[1] ==
'f') {
16610 int RegNum =
atoi(Constraint.
data() + 2);
16611 if (RegNum > 31 || RegNum < 0)
16613 if (VT == MVT::f32 || VT == MVT::i32)
16614 return Subtarget.hasSPE()
16615 ? std::make_pair(PPC::R0 + RegNum, &PPC::GPRCRegClass)
16616 : std::make_pair(PPC::F0 + RegNum, &PPC::F4RCRegClass);
16617 if (VT == MVT::f64 || VT == MVT::i64)
16618 return Subtarget.hasSPE()
16619 ? std::make_pair(PPC::S0 + RegNum, &PPC::SPERCRegClass)
16620 : std::make_pair(PPC::F0 + RegNum, &PPC::F8RCRegClass);
16624 std::pair<unsigned, const TargetRegisterClass *> R =
16633 if (R.first && VT == MVT::i64 && Subtarget.
isPPC64() &&
16634 PPC::GPRCRegClass.contains(R.first))
16635 return std::make_pair(
TRI->getMatchingSuperReg(R.first,
16636 PPC::sub_32, &PPC::G8RCRegClass),
16637 &PPC::G8RCRegClass);
16640 if (!R.second &&
StringRef(
"{cc}").equals_insensitive(Constraint)) {
16641 R.first = PPC::CR0;
16642 R.second = &PPC::CRRCRegClass;
16646 if (Subtarget.
isAIXABI() && !
TM.getAIXExtendedAltivecABI()) {
16647 if (((R.first >= PPC::V20 && R.first <= PPC::V31) ||
16648 (R.first >= PPC::VF20 && R.first <= PPC::VF31)) &&
16649 (R.second == &PPC::VSRCRegClass || R.second == &PPC::VSFRCRegClass))
16650 errs() <<
"warning: vector registers 20 to 32 are reserved in the "
16651 "default AIX AltiVec ABI and cannot be used\n";
16660 std::string &Constraint,
16661 std::vector<SDValue>&Ops,
16666 if (Constraint.length() > 1)
return;
16668 char Letter = Constraint[0];
16682 int64_t
Value =
CST->getSExtValue();
16724 if (Result.getNode()) {
16725 Ops.push_back(Result);
16736 if (
I.getNumOperands() <= 1)
16741 if (IntrinsicID != Intrinsic::ppc_tdw && IntrinsicID != Intrinsic::ppc_tw &&
16742 IntrinsicID != Intrinsic::ppc_trapd && IntrinsicID != Intrinsic::ppc_trap)
16745 if (
I.hasMetadata(
"annotation")) {
16763 if (Ty->isVectorTy() && AM.
BaseOffs != 0 && !Subtarget.hasP9Vector())
16775 switch (AM.
Scale) {
16812 bool isPPC64 = Subtarget.
isPPC64();
16824 isPPC64 ? MVT::i64 :
MVT::
i32);
16846 bool isPPC64 =
PtrVT == MVT::i64;
16852 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
16854 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
16868 bool isPPC64 = Subtarget.
isPPC64();
16875 .Case(
"r1",
is64Bit ? PPC::X1 : PPC::R1)
16876 .Case(
"r2", isPPC64 ?
Register() : PPC::R2)
16877 .Case(
"r13", (
is64Bit ? PPC::X13 : PPC::R13))
16920 unsigned Intrinsic)
const {
16921 switch (Intrinsic) {
16922 case Intrinsic::ppc_atomicrmw_xchg_i128:
16923 case Intrinsic::ppc_atomicrmw_add_i128:
16924 case Intrinsic::ppc_atomicrmw_sub_i128:
16925 case Intrinsic::ppc_atomicrmw_nand_i128:
16926 case Intrinsic::ppc_atomicrmw_and_i128:
16927 case Intrinsic::ppc_atomicrmw_or_i128:
16928 case Intrinsic::ppc_atomicrmw_xor_i128:
16929 case Intrinsic::ppc_cmpxchg_i128:
16931 Info.memVT = MVT::i128;
16932 Info.ptrVal =
I.getArgOperand(0);
16934 Info.align =
Align(16);
16938 case Intrinsic::ppc_atomic_load_i128:
16940 Info.memVT = MVT::i128;
16941 Info.ptrVal =
I.getArgOperand(0);
16943 Info.align =
Align(16);
16946 case Intrinsic::ppc_atomic_store_i128:
16948 Info.memVT = MVT::i128;
16949 Info.ptrVal =
I.getArgOperand(2);
16951 Info.align =
Align(16);
16954 case Intrinsic::ppc_altivec_lvx:
16955 case Intrinsic::ppc_altivec_lvxl:
16956 case Intrinsic::ppc_altivec_lvebx:
16957 case Intrinsic::ppc_altivec_lvehx:
16958 case Intrinsic::ppc_altivec_lvewx:
16959 case Intrinsic::ppc_vsx_lxvd2x:
16960 case Intrinsic::ppc_vsx_lxvw4x:
16961 case Intrinsic::ppc_vsx_lxvd2x_be:
16962 case Intrinsic::ppc_vsx_lxvw4x_be:
16963 case Intrinsic::ppc_vsx_lxvl:
16964 case Intrinsic::ppc_vsx_lxvll: {
16966 switch (Intrinsic) {
16967 case Intrinsic::ppc_altivec_lvebx:
16970 case Intrinsic::ppc_altivec_lvehx:
16973 case Intrinsic::ppc_altivec_lvewx:
16976 case Intrinsic::ppc_vsx_lxvd2x:
16977 case Intrinsic::ppc_vsx_lxvd2x_be:
16987 Info.ptrVal =
I.getArgOperand(0);
16990 Info.align =
Align(1);
16994 case Intrinsic::ppc_altivec_stvx:
16995 case Intrinsic::ppc_altivec_stvxl:
16996 case Intrinsic::ppc_altivec_stvebx:
16997 case Intrinsic::ppc_altivec_stvehx:
16998 case Intrinsic::ppc_altivec_stvewx:
16999 case Intrinsic::ppc_vsx_stxvd2x:
17000 case Intrinsic::ppc_vsx_stxvw4x:
17001 case Intrinsic::ppc_vsx_stxvd2x_be:
17002 case Intrinsic::ppc_vsx_stxvw4x_be:
17003 case Intrinsic::ppc_vsx_stxvl:
17004 case Intrinsic::ppc_vsx_stxvll: {
17006 switch (Intrinsic) {
17007 case Intrinsic::ppc_altivec_stvebx:
17010 case Intrinsic::ppc_altivec_stvehx:
17013 case Intrinsic::ppc_altivec_stvewx:
17016 case Intrinsic::ppc_vsx_stxvd2x:
17017 case Intrinsic::ppc_vsx_stxvd2x_be:
17027 Info.ptrVal =
I.getArgOperand(1);
17030 Info.align =
Align(1);
17034 case Intrinsic::ppc_stdcx:
17035 case Intrinsic::ppc_stwcx:
17036 case Intrinsic::ppc_sthcx:
17037 case Intrinsic::ppc_stbcx: {
17039 auto Alignment =
Align(8);
17040 switch (Intrinsic) {
17041 case Intrinsic::ppc_stdcx:
17044 case Intrinsic::ppc_stwcx:
17046 Alignment =
Align(4);
17048 case Intrinsic::ppc_sthcx:
17050 Alignment =
Align(2);
17052 case Intrinsic::ppc_stbcx:
17054 Alignment =
Align(1);
17059 Info.ptrVal =
I.getArgOperand(0);
17061 Info.align = Alignment;
17079 if (Subtarget.hasAltivec() &&
Op.size() >= 16 &&
17081 ((
Op.isMemset() && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
17096 assert(Ty->isIntegerTy());
17098 unsigned BitSize = Ty->getPrimitiveSizeInBits();
17099 return !(BitSize == 0 || BitSize > 64);
17103 if (!
Ty1->isIntegerTy() || !
Ty2->isIntegerTy())
17105 unsigned NumBits1 =
Ty1->getPrimitiveSizeInBits();
17106 unsigned NumBits2 =
Ty2->getPrimitiveSizeInBits();
17111 if (!
VT1.isInteger() || !
VT2.isInteger())
17140 "invalid fpext types");
17142 if (
DestVT == MVT::f128)
17157 unsigned *
Fast)
const {
17171 !Subtarget.allowsUnalignedFPAccess())
17175 if (Subtarget.hasVSX()) {
17176 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
17177 VT != MVT::v4f32 && VT != MVT::v4i32)
17184 if (VT == MVT::ppcf128)
17199 if (!
ConstNode->getAPIntValue().isSignedIntN(64))
17207 int64_t Imm =
ConstNode->getSExtValue();
17228 if (Subtarget.hasSPE())
17230 switch (Ty->getScalarType()->getTypeID()) {
17235 return Subtarget.hasP9Vector();
17243 if (!
I->hasOneUse())
17247 assert(
User &&
"A single use instruction with no uses.");
17249 switch (
I->getOpcode()) {
17250 case Instruction::FMul: {
17252 if (
User->getOpcode() != Instruction::FSub &&
17253 User->getOpcode() != Instruction::FAdd)
17266 case Instruction::Load: {
17279 if (
User->getOpcode() != Instruction::Store)
17300 PPC::X12, PPC::LR8, PPC::CTR8, 0
17307 const Constant *PersonalityFn)
const {
17308 return Subtarget.
isPPC64() ? PPC::X3 : PPC::R3;
17312 const Constant *PersonalityFn)
const {
17313 return Subtarget.
isPPC64() ? PPC::X4 : PPC::R4;
17318 EVT VT ,
unsigned DefinedValues)
const {
17319 if (VT == MVT::v2i64)
17320 return Subtarget.hasDirectMove();
17322 if (Subtarget.hasVSX())
17356 bool LegalOps,
bool OptForSize,
17358 unsigned Depth)
const {
17362 unsigned Opc =
Op.getOpcode();
17363 EVT VT =
Op.getValueType();
17388 if (Flags.hasNoSignedZeros() ||
Options.NoSignedZerosFPMath) {
17401 }
else if (
NegN1) {
17446 bool ForCodeSize)
const {
17447 if (!VT.
isSimple() || !Subtarget.hasVSX())
17457 if (Subtarget.hasPrefixInstrs()) {
17469 return Imm.isZero();
17472 return Imm.isPosZero();
17484 unsigned Opcode =
N->getOpcode();
17485 unsigned TargetOpcode;
17505 return DAG.
getNode(TargetOpcode,
SDLoc(
N), VT, N0,
N1->getOperand(0));
17516 if (!Subtarget.isISA3_0() || !Subtarget.
isPPC64() ||
17519 N->getValueType(0) != MVT::i64)
17533 if (
ShiftBy.getValueType() == MVT::i64)
17568 Op.getValueType() != MVT::i64)
17572 if (Cmp.getOpcode() !=
ISD::SETCC || !Cmp.hasOneUse() ||
17573 Cmp.getOperand(0).getValueType() != MVT::i64)
17597 SDValue Cmp = RHS.getOperand(0);
17598 SDValue Z = Cmp.getOperand(0);
17705 DAGCombinerInfo &
DCI)
const {
17707 if (Subtarget.useCRBits()) {
17717 if (Op0.
getValueType() != MVT::i128 ||
N->getValueType(0) != MVT::i64)
17740 return DCI.DAG.getNode(
17786 EVT VT =
N->getValueType(0);
17810 }
else if ((
MulAmtAbs + 1).isPowerOf2()) {
17835 DAGCombinerInfo &
DCI)
const {
17840 EVT VT =
N->getValueType(0);
17843 unsigned Opc =
N->getOpcode();
17845 bool LegalOps = !
DCI.isBeforeLegalizeOps();
17853 if (!Flags.hasNoSignedZeros() && !
Options.NoSignedZerosFPMath)
17869bool PPCTargetLowering::mayBeEmittedAsTailCall(
const CallInst *CI)
const {
17899bool PPCTargetLowering::
17905 if (CI->getBitWidth() > 64)
17907 int64_t ConstVal = CI->getZExtValue();
17909 (
isUInt<16>(ConstVal >> 16) && !(ConstVal & 0xFFFF));
17918PPC::AddrMode PPCTargetLowering::getAddrModeForFlags(
unsigned Flags)
const {
17977 if ((Imm & 0x3) == 0)
17979 if ((Imm & 0xf) == 0)
18035unsigned PPCTargetLowering::computeMOFlags(
const SDNode *Parent,
SDValue N,
18040 if (!Subtarget.hasP9Vector())
18044 if (Subtarget.hasPrefixInstrs())
18047 if (Subtarget.hasSPE())
18060 if ((
ID == Intrinsic::ppc_vsx_lxvp) || (
ID == Intrinsic::ppc_vsx_stxvp)) {
18073 if (LSB->isIndexed())
18079 assert(
MN &&
"Parent should be a MemSDNode!");
18082 if (
MemVT.isScalarInteger()) {
18084 "Not expecting scalar integers larger than 16 bytes!");
18087 else if (
Size == 32)
18091 }
else if (
MemVT.isVector() && !
MemVT.isFloatingPoint()) {
18094 else if (
Size == 256) {
18095 assert(Subtarget.pairedVectorMemops() &&
18096 "256-bit vectors are only available when paired vector memops is "
18104 else if (
MemVT == MVT::f128 ||
MemVT.isVector())
18115 switch (
LN->getExtensionType()) {
18172 !
N.getOperand(1).hasOneUse() || !
N.getOperand(0).hasOneUse())) {
18194 if (
PartVT == MVT::f64 &&
18195 (ValVT == MVT::i32 || ValVT == MVT::i16 || ValVT == MVT::i8)) {
18216 EVT ArgVT =
N.getValueType();
18221 Entry.IsZExt = !Entry.IsSExt;
18222 Args.push_back(Entry);
18230 (
RetTy ==
F.getReturnType() ||
F.getReturnType()->isVoidTy());
18236 .setTailCall(isTailCall)
18243SDValue PPCTargetLowering::lowerLibCallBasedOnType(
18246 if (
Op.getValueType() == MVT::f32)
18249 if (
Op.getValueType() == MVT::f64)
18255bool PPCTargetLowering::isLowringToMASSFiniteSafe(
SDValue Op)
const {
18257 return isLowringToMASSSafe(
Op) && Flags.hasNoSignedZeros() &&
18258 Flags.hasNoNaNs() && Flags.hasNoInfs();
18261bool PPCTargetLowering::isLowringToMASSSafe(
SDValue Op)
const {
18262 return Op.getNode()->getFlags().hasApproximateFuncs();
18265bool PPCTargetLowering::isScalarMASSConversionEnabled()
const {
18275 if (!isScalarMASSConversionEnabled() || !isLowringToMASSSafe(
Op))
18278 if (!isLowringToMASSFiniteSafe(
Op))
18287 return lowerLibCallBase(
"__xl_pow",
"__xl_powf",
"__xl_pow_finite",
18288 "__xl_powf_finite",
Op, DAG);
18292 return lowerLibCallBase(
"__xl_sin",
"__xl_sinf",
"__xl_sin_finite",
18293 "__xl_sinf_finite",
Op, DAG);
18297 return lowerLibCallBase(
"__xl_cos",
"__xl_cosf",
"__xl_cos_finite",
18298 "__xl_cosf_finite",
Op, DAG);
18302 return lowerLibCallBase(
"__xl_log",
"__xl_logf",
"__xl_log_finite",
18303 "__xl_logf_finite",
Op, DAG);
18307 return lowerLibCallBase(
"__xl_log10",
"__xl_log10f",
"__xl_log10_finite",
18308 "__xl_log10f_finite",
Op, DAG);
18312 return lowerLibCallBase(
"__xl_exp",
"__xl_expf",
"__xl_exp_finite",
18313 "__xl_expf_finite",
Op, DAG);
18338 unsigned Flags = computeMOFlags(Parent,
N, DAG);
18350 "Must be using PC-Relative calls when a valid PC-Relative node is "
18385 Base =
N.getOperand(0);
18428 unsigned Opcode =
N.getOpcode();
18467 bool IsVarArg)
const {
18477 return Subtarget.
isPPC64() && Subtarget.hasQuadwordAtomics();
18511 return Intrinsic::ppc_atomicrmw_xchg_i128;
18513 return Intrinsic::ppc_atomicrmw_add_i128;
18515 return Intrinsic::ppc_atomicrmw_sub_i128;
18517 return Intrinsic::ppc_atomicrmw_and_i128;
18519 return Intrinsic::ppc_atomicrmw_or_i128;
18521 return Intrinsic::ppc_atomicrmw_xor_i128;
18523 return Intrinsic::ppc_atomicrmw_nand_i128;
18531 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18533 assert(ValTy->getPrimitiveSizeInBits() == 128);
18539 Builder.CreateTrunc(Builder.CreateLShr(
Incr, 64), Int64Ty,
"incr_hi");
18543 Value *
Lo = Builder.CreateExtractValue(
LoHi, 0,
"lo");
18544 Value *
Hi = Builder.CreateExtractValue(
LoHi, 1,
"hi");
18545 Lo = Builder.CreateZExt(
Lo, ValTy,
"lo64");
18546 Hi = Builder.CreateZExt(
Hi, ValTy,
"hi64");
18547 return Builder.CreateOr(
18555 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18557 assert(ValTy->getPrimitiveSizeInBits() == 128);
18563 Builder.CreateTrunc(Builder.CreateLShr(
CmpVal, 64), Int64Ty,
"cmp_hi");
18566 Builder.CreateTrunc(Builder.CreateLShr(
NewVal, 64), Int64Ty,
"new_hi");
18573 Value *
Lo = Builder.CreateExtractValue(
LoHi, 0,
"lo");
18574 Value *
Hi = Builder.CreateExtractValue(
LoHi, 1,
"hi");
18575 Lo = Builder.CreateZExt(
Lo, ValTy,
"lo64");
18576 Hi = Builder.CreateZExt(
Hi, ValTy,
"hi64");
18577 return Builder.CreateOr(
unsigned const MachineRegisterInfo * MRI
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
static SDValue GeneratePerfectShuffle(unsigned ID, SDValue V1, SDValue V2, unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations t...
static bool isSignExtended(SDNode *N, SelectionDAG &DAG)
static const unsigned PerfectShuffleTable[6561+1]
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
static bool isLoad(int Opcode)
static bool isFloatingPointZero(SDValue Op)
isFloatingPointZero - Return true if this is +0.0.
Function Alias Analysis Results
Atomic ordering constants.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
This file defines the DenseMap class.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static bool isSplat(Value *V)
Return true if V is a splat of a value (which is used when multiplying a matrix with a scalar).
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
static bool isConstantOrUndef(const SDValue Op)
Module.h This file contains the declarations for the Module class.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
cl::opt< bool > ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
static SDValue getCanonicalConstSplat(uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.
static const TargetRegisterClass * getRegClassForSVT(MVT::SimpleValueType SVT, bool IsPPC64, bool HasP8Vector, bool HasVSX)
static bool isGPRShadowAligned(MCPhysReg Reg, Align RequiredAlign)
static bool needStackSlotPassParameters(const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs)
static bool isAlternatingShuffMask(const ArrayRef< int > &Mask, int NumElts)
static SDValue addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems)
static cl::opt< bool > DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG)
static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG)
This function is called when we have proved that a SETCC node can be replaced by subtraction (and oth...
static unsigned mapArgRegToOffsetAIX(unsigned Reg, const PPCFrameLowering *FL)
static SDValue combineADDToMAT_PCREL_ADDR(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static void setAlignFlagsForFI(SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
Set alignment flags based on whether or not the Frame Index is aligned.
static bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget)
static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N)
Used when computing address flags for selecting loads and stores.
static void CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
CalculateTailCallArgDest - Remember Argument for later processing.
static bool callsShareTOCBase(const Function *Caller, const GlobalValue *CalleeGV, const TargetMachine &TM)
static bool isPCRelNode(SDValue N)
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
static bool areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC, CallingConv::ID CalleeCC)
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
static SDNode * isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG)
isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable ...
static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.
static bool haveEfficientBuildVectorPattern(BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector)
Do we have an efficient pattern in a .td file for this node?
static SDValue getSToVPermuted(SDValue OrigSToV, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &S)
static void setUsesTOCBasePtr(MachineFunction &MF)
static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget)
static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering, unsigned NumBytes)
EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required f...
static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static bool isStoreConditional(SDValue Intrin, unsigned &StoreWidth)
static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB)
static bool isFPExtLoad(SDValue Op)
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.
static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static void StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl)
StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static const char AIXSSPCanaryWordName[]
static cl::opt< bool > UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)
static void setXFormForUnalignedFI(SDValue N, unsigned Flags, PPC::AddrMode &Mode)
static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign)
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment...
static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
isVMerge - Common function, used to match vmrg* shuffles.
static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the tar...
cl::opt< bool > DisableAutoPairedVecSt("disable-auto-paired-vec-st", cl::desc("disable automatically generated 32byte paired vector stores"), cl::init(true), cl::Hidden)
static void buildCallOperands(SmallVectorImpl< SDValue > &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget)
static cl::opt< bool > DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)
static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget &ST)
Returns true if we should use a direct load into vector instruction (such as lxsd or lfd),...
static SDValue getDataClassTest(SDValue Op, FPClassTest Mask, const SDLoc &Dl, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static cl::opt< bool > DisableSCO("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)
static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT)
static cl::opt< bool > DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
static Intrinsic::ID getIntrinsicForAtomicRMWBinOp128(AtomicRMWInst::BinOp BinOp)
static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.
static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the argu...
static Instruction * callIntrinsic(IRBuilderBase &Builder, Intrinsic::ID Id)
static void fixupShuffleMaskForPermutedSToV(SmallVectorImpl< int > &ShuffV, int LHSMaxIdx, int RHSMinIdx, int RHSMaxIdx, int HalfVec, unsigned ValidLaneWidth, const PPCSubtarget &Subtarget)
static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl)
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
static SDValue isScalarToVec(SDValue Op)
static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl)
static cl::opt< bool > DisablePerfectShuffle("ppc-disable-perfect-shuffle", cl::desc("disable vector permute decomposition"), cl::init(true), cl::Hidden)
static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.
static unsigned invertFMAOpcode(unsigned Opc)
static const SDValue * getNormalLoadInput(const SDValue &Op, bool &IsPermuted)
static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op, unsigned &Opcode)
static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG, const PPCSubtarget &Subtarget, SDValue Chain=SDValue())
static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget)
static void PrepareTailCall(SelectionDAG &DAG, SDValue &InGlue, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl)
EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack sl...
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.
static SDValue combineBVZEXTLOAD(SDNode *N, SelectionDAG &DAG)
static SDValue truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl)
static void computeFlagsForAddressComputation(SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
Given a node, compute flags that are used for address computation when selecting load and store instr...
cl::opt< bool > ANDIGlueBug
static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart)
static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs)
CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passe...
static unsigned getPPCStrictOpcode(unsigned Opc)
static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget)
static bool isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width)
static bool isFunctionGlobalAddress(const GlobalValue *CalleeGV)
static bool isSplatBV(SDValue Op)
static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG)
static cl::opt< bool > DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int)
Check that the mask is shuffling N byte elements.
static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG)
Reduce the number of loads when building a vector.
static bool isValidPCRelNode(SDValue N)
const char LLVMTargetMachineRef TM
pre isel intrinsic Pre ISel Intrinsic Lowering
const SmallVectorImpl< MachineOperand > & Cond
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
This file describes how to lower LLVM code to machine code.
This defines the Use class.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool is64Bit(const char *name)
Class for arbitrary precision integers.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
bool isNegatedPowerOf2() const
Check if this APInt's negated value is a power of two greater than zero.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
An arbitrary precision integer that knows its signedness.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
An instruction that atomically checks whether a specified value is in a memory location,...
Value * getNewValOperand()
an instruction that atomically reads a memory location, combines it with another value,...
BinOp
This enumeration lists the possible modifications atomicrmw can make.
@ UIncWrap
Increment one up to a maximum value.
@ UDecWrap
Decrement one until a minimum value or zero.
BinOp getOperation() const
This is an SDNode representing atomic operations.
StringRef getValueAsString() const
Return the attribute's value as a string.
LLVM Basic Block Representation.
const Function * getParent() const
Return the enclosing method, or null if none.
The address of a basic block.
static BranchProbability getOne()
static BranchProbability getZero()
A "pseudo-class" with methods for operating on BUILD_VECTORs.
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
bool isStrictFP() const
Determine if the call requires strict floating point semantics.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Value * getCalledOperand() const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
unsigned arg_size() const
Function * getCaller()
Helper to get the caller (the parent function).
This class represents a function call, abstracting a target machine's calling convention.
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
uint64_t getFnAttributeAsParsedInteger(StringRef Kind, uint64_t Default=0) const
For a string attribute Kind, parse attribute as an integer.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const Function & getFunction() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalObject * getAliaseeObject() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Module * getParent()
Get the module that this global value is contained inside of...
Type * getValueType() const
Common base class shared among various IRBuilders.
@ Kind_RegDefEarlyClobber
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
static unsigned getKind(unsigned Flags)
const BasicBlock * getParent() const
bool hasAtomicLoad() const LLVM_READONLY
Return true if this atomic instruction loads from memory.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
This is an important class for using LLVM in a threaded context.
Base class for LoadSDNode and StoreSDNode.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
Wrapper class representing physical registers. Should be passed by value.
MCSymbolXCOFF * getQualNameSymbol() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
@ INVALID_SIMPLE_VALUE_TYPE
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool hasVAStart() const
Returns true if the function calls the llvm.va_start intrinsic.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
BasicBlockListType::iterator iterator
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
@ EK_LabelDifference32
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table.
A description of a memory reference used in the backend.
uint64_t getSize() const
Return the size in bytes of the memory reference.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
An SDNode that represents everything that will be needed to construct a MachineInstr.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
This is an abstract virtual class for memory operations.
A Module instance is used to store all the information related to an LLVM module.
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
void setVarArgsNumFPR(unsigned Num)
void setReturnAddrSaveIndex(int idx)
int getReturnAddrSaveIndex() const
unsigned getVarArgsNumFPR() const
int getFramePointerSaveIndex() const
void setVarArgsNumGPR(unsigned Num)
void appendParameterType(ParamType Type)
int getVarArgsFrameIndex() const
void setLRStoreRequired()
void setTailCallSPDelta(int size)
bool isLRStoreRequired() const
void setMinReservedArea(unsigned size)
unsigned getVarArgsNumGPR() const
unsigned getMinReservedArea() const
void setVarArgsStackOffset(int Offset)
void setVarArgsFrameIndex(int Index)
void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags)
This function associates attributes for each live-in virtual register.
int getVarArgsStackOffset() const
void setFramePointerSaveIndex(int Idx)
bool is32BitELFABI() const
unsigned descriptorTOCAnchorOffset() const
bool useSoftFloat() const
const PPCFrameLowering * getFrameLowering() const override
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
bool isUsingPCRelativeCalls() const
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
MCRegister getEnvironmentPointerRegister() const
const PPCInstrInfo * getInstrInfo() const override
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
POPCNTDKind hasPOPCNTD() const
bool isLittleEndian() const
bool isTargetLinux() const
MCRegister getTOCPointerRegister() const
MCRegister getStackPointerRegister() const
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
bool isPredictableSelectIsExpensive() const
bool enableMachineScheduler() const override
Scheduling customization.
const PPCRegisterInfo * getRegisterInfo() const override
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned descriptorEnvironmentPointerOffset() const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
bool supportsTailCallFor(const CallBase *CB) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=std::nullopt) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
bool useSoftFloat() const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
unsigned getStackProbeSize(const MachineFunction &MF) const
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const
Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isJumpTableRelative() const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const
SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isAccessedAsGotIndirect(SDValue N) const
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
bool shouldInlineQuadwordAtomics() const
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool hasOneUse() const
Return true if there is exactly one use of this node.
SDNodeFlags getFlags() const
const SDValue & getOperand(unsigned Num) const
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isPredecessorOf(const SDNode *N) const
Return true if this node is a predecessor of N.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
static use_iterator use_end()
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
unsigned getNumOperands() const
static SectionKind getMetadata()
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
const TargetLowering & getTargetLoweringInfo() const
static constexpr unsigned MaxRecursionDepth
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Class to represent struct types.
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
NegatibleCost
Enum that specifies when a float negation is beneficial.
std::vector< ArgListEntry > ArgListTy
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
virtual MCSymbol * getFunctionEntryPointSymbol(const GlobalValue *Func, const TargetMachine &TM) const
If supported, return the function entry point symbol.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const
Soften the operands of a comparison.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression only when the cost is cheaper.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) const
Return a target-dependent comparison result if the input operand is suitable for use with a square ro...
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
virtual SDValue getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const
Return a target-dependent result if the input operand is not suitable for use with a square root esti...
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
unsigned PPCGenScalarMASSEntries
Enables scalar MASS conversions.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize Fixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
static IntegerType * getInt64Ty(LLVMContext &C)
@ FloatTyID
32-bit floating point type
@ DoubleTyID
64-bit floating point type
@ FP128TyID
128-bit floating point type (112-bit significand)
static Type * getVoidTy(LLVMContext &C)
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
bool isFunctionTy() const
True if this is an instance of FunctionType.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
unsigned getNumOperands() const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
Implementation for an ilist node.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ FADD
Simple binary floating point operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ BR
Control flow instructions. These all have token chains.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=std::nullopt)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
@ Bitcast
Perform the operation on a different, but equivalently sized type.
@ MO_GOT_TPREL_PCREL_FLAG
MO_GOT_TPREL_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
@ MO_TLSGDM_FLAG
MO_TLSGDM_FLAG - If this bit is set the symbol reference is relative to the region handle of TLS Gene...
@ MO_PCREL_FLAG
MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...
@ MO_GOT_FLAG
MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.
@ MO_PLT
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
@ MO_TPREL_FLAG
MO_TPREL_FLAG - If this bit is set, the symbol reference is relative to the thread pointer and the sy...
@ MO_LO
MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
@ MO_GOT_TLSLD_PCREL_FLAG
MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
@ MO_TLSGD_FLAG
MO_TLSGD_FLAG - If this bit is set the symbol reference is relative to TLS General Dynamic model for ...
@ MO_GOT_TLSGD_PCREL_FLAG
MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
@ MO_PIC_FLAG
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function's picbase,...
@ SEXT_LD_SPLAT
VSRC, CHAIN = SEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that sign-extends.
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
@ FSQRT
Square root instruction.
@ STRICT_FCFID
Constrained integer-to-floating-point conversion instructions.
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
@ CALL_RM
The variants that implicitly define rounding mode for calls with strictfp semantics.
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
@ SRL
These nodes represent PPC shifts.
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
@ FRE
Reciprocal estimate instructions (unary FP ops).
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
@ STORE_COND
CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr The store conditional instruction ST[BHWD]ARX that produces a...
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
@ RET_GLUE
Return with a glue operand, matched by 'blr'.
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
@ EXTRACT_VSX_REG
EXTRACT_VSX_REG = Extract one of the underlying vsx registers of an accumulator or pair register.
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Can be used by the initial-exec and local-exec TLS models,...
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
@ ACC_BUILD
ACC_BUILD = Build an accumulator register from 4 VSX registers.
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
@ XSMAXC
XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
@ CALL
CALL - A direct function call.
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
@ TC_RETURN
TC_RETURN - A tail call return.
@ STFIWX
STFIWX - The STFIWX instruction.
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
@ VCMP_rec
RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the altivec VCMP*_rec instructions.
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
@ PADDI_DTPREL
G8RC = PADDI_DTPREL x3, Symbol - For the pc-rel based local-dynamic TLS model, produces a PADDI8 inst...
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
@ TLS_LOCAL_EXEC_MAT_ADDR
TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address when using local exec access ...
@ VPERM
VPERM - The PPC VPERM Instruction.
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
@ PAIR_BUILD
PAIR_BUILD = Build a vector pair register from 2 VSX registers.
@ STRICT_FADDRTZ
Constrained floating point add in round-to-zero mode.
@ FTSQRT
Test instruction for software square root.
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
@ VECSHL
VECSHL - The PPC vector shift left instruction.
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
@ ZEXT_LD_SPLAT
VSRC, CHAIN = ZEXT_LD_SPLAT, CHAIN, Ptr - a splatting load memory that zero-extends.
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
@ TLSGD_AIX
GPRC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY Op that combines two re...
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
@ GET_TPOINTER
x3 = GET_TPOINTER - Used for the local-exec TLS model on 32-bit AIX, produces a call to ....
@ LXVRZX
LXVRZX - Load VSX Vector Rightmost and Zero Extend This node represents v1i128 BUILD_VECTOR of a zero...
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
@ FSEL
FSEL - Traditional three-operand fsel node.
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
@ MFVSR
Direct move from a VSX register to a GPR.
@ TLS_DYNAMIC_MAT_PCREL_ADDR
TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for TLS global address when using dyna...
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
@ Define
Register definition.
@ XTY_ER
External reference.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
static bool isIndirectCall(const MachineInstr &MI)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
unsigned M1(unsigned Val)
bool isReleaseOrStronger(AtomicOrdering AO)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
bool convertToNonDenormSingle(APInt &ArgAPInt)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool CC_PPC64_ELF(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Mod
The access may modify the value stored in memory.
bool isIntS34Immediate(SDNode *N, int64_t &Imm)
isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ Mul
Product of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
DWARFExpression::Operation Op
unsigned M0(unsigned Val)
ArrayRef(const T &OneElt) -> ArrayRef< T >
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
bool isAcquireOrStronger(AtomicOrdering AO)
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
constexpr unsigned BitWidth
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This is used by foldLoadsRecursive() to capture a Root Load node which is of type or(load,...
static const fltSemantics & IEEEsingle() LLVM_READNONE
static constexpr roundingMode rmNearestTiesToEven
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
static constexpr roundingMode rmTowardZero
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
Represent subnormal handling kind for floating point instruction inputs and outputs.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
void resetAll()
Resets the known state of all bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Structure that collects some common arguments that get passed around between the functions for call l...
These are IR-level optimization flags that may be propagated to SDNodes.
void setNoFPExcept(bool b)
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setZExtResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setSExtResult(bool Value=true)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals